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Philips Semiconductors
UART
BRGCON
Address: BDh
Not bit addressable
Reset Source(s): Any reset
Reset Value: xxxxxx00B
BIT
SYMBOL
BRGCON.7-2
-
BRGCON.1
SBRGS
BRGCON.0
BRGEN
Timer 1 Overflow
(PCLK-based)
Baud Rate Generator
(CCLK-based)
Framing Error
A Framing error occurs when the stop bit is sensed as a logic '0'. A Framing error is reported in the status register (SSTAT). In
addition, if SMOD0 (PCON.6) is 1, framing errors can be made available in SCON.7. If SMOD0 is 0, SCON.7 is SM0. It is
recommended that SM0 and SM1 (SCON.7-6) are programmed when SMOD0 is '0'.
Break Detect
A break detect is reported in the status register (SSTAT). A break is detected when any 11 consecutive bits are sensed low.
Since a break condition also satisfies the requirements for a framing error, a break condition will also result in reporting a framing
error. Once a break condition has been detected, the UART will go into an idle state and remain in this idle state until a stop bit
has been received. The break detect can be used to reset the device and force the device into ISP mode by setting the EBRR
bit (AUXR1.6)
2003 Dec 8
7
6
-
-
FUNCTION
Reserved for future use. Should not be set to 1 by user programs.
Select Baud Rate Generator as the source for baud rates to UART in modes 1 & 3 (see
Table 9-2 for details)
Baud Rate Generator Enable. Enables the baud rate generator. BRGR1 and BRGR0 can
only be written when BRGEN =0.
Figure 9-1: BRGCON register
SMOD1 = 1
÷2
SMOD1 = 0
Figure 9-2: Baud rate generation for UART (Modes 1, 3)
5
4
3
-
-
-
SBRGS = 0
Baud Rate Modes 1 and 3
SBRGS = 1
53
User's Manual - Preliminary -
P89LPC920/921/922
2
1
0
-
SBRGS BRGEN
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