Usb Device Interrupt Enable Register (Usbdevinten - 0Xe009 0004); Usb Device Interrupt Clear Register (Usbdevintclr - 0Xe009 0008) - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1
Table 177: USB Device Interrupt Status register (USBDevIntSt - address 0xE009 0000) bit description
Bit Symbol Description
6 RxENDPKT The current packet in the FIFO is transferred to the CPU.
7 TxENDPKT The number of data bytes transferred to the FIFO equals the number of bytes
programmed in the TxPacket length register.
8 EP_RLZED Endpoints realized. Set when Realize endpoint register or Maxpacket size register is
updated.
9 ERR_INT Error Interrupt. Any bus error interrupt from the USB device. Refer to
"Read Error Status (Command: 0xFB, Data: read 1 byte)" on page 227
31:10 - Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.

14.7.3 USB Device Interrupt Enable register (USBDevIntEn - 0xE009 0004)

If the Interrupt Enable bit value is set, an interrupt is generated (on Fast or Slow Interrupt
line) when the corresponding bit in the Device Interrupt Status register is set
(Section
held in the interrupt status register. All bits of this register are cleared after reset. The
USBDevIntEn is a read/write register.
Table 178: USB Device Interrupt Enable register (USBDevIntEn - address 0xE009 0004) bit allocation
Reset value: 0x0000 0000
Bit 31
Symbol -
Bit 23
Symbol -
Bit 15
Symbol -
Bit 7
Symbol TxENDPKT
Table 179: USB Device Interrupt Enable register (USBDevIntEn - address 0xE009 0004) bit description
Bit Symbol Value
31:0 See 0
USBDevIntEn
1
bit allocation
table above

14.7.4 USB Device Interrupt Clear register (USBDevIntClr - 0xE009 0008)

Setting a particular bit to 1 in this register causes the clearing of the interrupt by resetting
the corresponding bit in the interrupt status register. Writing a 0 will not have any
influence. The USBDevIntClr is a write only register.
Table 180: USB Device Interrupt Clear register (USBDevIntClr - address 0xE009 0008) bit allocation
Reset value: 0x0000 0000
Bit 31
Symbol -
9397 750 XXXXX
User manual
14.7.2). If it is not set, no external interrupt is generated but interrupt will still be
30 29
- -
22 21
- -
14 13
- -
6 5
Rx CDFULL
ENDPKT
Description
No external interrupt is generated.
Enables an external interrupt to be generated (Fast or Slow) when the
corresponding bit in the Device Interrupt Status register
set.
30 29
- -
Rev. 01 — 15 August 2005
Chapter 14: USB Device Controller
28 27
- -
20 19
- -
12 11
- -
4 3
CCEMTY DEV_STAT
28 27
- -
UM10139
Reset value
0
0
0
Section 14.9.9 0
NA
26 25
- -
18 17
- -
10 9
- EPR_INT
2 1
EP_SLOW EP_FAST
(Section 14.7.2) is
26 25
- -
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
24
-
16
-
8
EP_RLZED
0
FRAME
Reset value
0
24
-
202