Table of Contents
Advertisement
Philips Semiconductors
Volume 1
Table 6:
Name
CSPR
Syscon Miscellaneous Registers
SCS
[1]
3.4 Crystal oscillator
While an input signal of 50-50 duty cycle within a frequency range from 1 MHz to 50 MHz
can be used by the LPC2141/2/4/6/8 if supplied to its input XTAL1 pin, this
microcontroller's onboard oscillator circuit supports external crystals in the range of 1 MHz
to 30 MHz only. If the on-chip PLL system or the boot-loader is used, the input clock
frequency is limited to an exclusive range of 10 MHz to 25 MHz.
The oscillator output frequency is called F
referred to as CCLK for purposes of rate equations, etc. elsewhere in this document. F
and CCLK are the same value unless the PLL is running and connected. Refer to the
Section 3.8 "Phase Locked Loop (PLL)" on page 27
The onboard oscillator in the LPC2141/2/4/6/8 can operate in one of two modes: slave
mode and oscillation mode.
In slave mode the input clock signal should be coupled by means of a capacitor of 100 pF
(C
configuration can be left not connected. If slave mode is selected, the F
duty cycle can range from 1 MHz to 50 MHz.
External components and models used in oscillation mode are shown in
drawings b and c, and in
a crystal and the capacitances C
fundamental mode oscillation (the fundamental frequency is represented by L, C
R
and should not be larger than 7 pF. Parameters F
crystal manufacturer.
Choosing an oscillation mode as an on-board oscillator mode of operation limits F
clock selection to 1 MHz to 30 MHz.
User manual
Summary of system control registers
Description
Code Security Protection Register
System Controls and Status
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
in
Figure
6, drawing a), with an amplitude of at least 200 mVrms. The X2 pin in this
C
Table
). Capacitance C
in
Figure
S
P
Rev. 01 — 15 August 2005
Access
RO
R/W
and the ARM processor clock frequency is
OSC
for details and frequency limitations.
7. Since the feedback resistance is integrated on chip, only
and C
need to be connected externally in case of
X1
X2
6, drawing c, represents the parallel package capacitance
, C
C
L
UM10139
Chapter 3: System Control Block
Reset
Address
[1]
value
0
0xE01F C184
0
0xE01F C1A0
signal of 50-50
OSC
Figure
, R
and C
are supplied by the
S
P
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
OSC
6,
and
L
OSC
18
Advertisement
Table of Contents
