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Philips Semiconductors
Volume 1
The ARM7TDMI-S core has a Debug Communication Channel function in-built. The
debug communication channel allows a program running on the target to communicate
with the host debugger or another separate host without stopping the program flow or
even entering the debug state. The debug communication channel is accessed as a
co-processor 14 by the program running on the ARM7TDMI-S core. The debug
communication channel allows the JTAG port to be used for sending and receiving data
without affecting the normal program flow. The debug communication channel data and
control registers are mapped in to addresses in the EmbeddedICE logic.
22.4 Pin description
Table 315: EmbeddedICE pin description
Pin Name
TMS
TCK
TDI
TDO
nTRST
RTCK
22.5 Reset state of multiplexed pins
On the LPC2141/2/4/6/8, the pins above are multiplexed with P1.31-26. To have them
come up as a Debug port, connect a weak bias resistor (4.7-10 kΩ depending on the
external JTAG circuitry) between V
GPIO pins, do not connect a bias resistor, and ensure that any external driver connected
to P1.26/RTCK is either driving high, or is in high-impedance state, during Reset.
User manual
trigger on an access to a peripheral and the second to trigger on the code segment
that performs the task switching. Therefore when the breakpoints trigger the
information regarding which task has switched out will be ready for examination.
•
The watchpoints can be configured such that a range of addresses are enabled for
the watchpoints to be active. The RANGE function allows the breakpoints to be
combined such that a breakpoint is to occur if an access occurs in the bottom 256
bytes of memory but not in the bottom 32 bytes.
Type
Description
Input
Test Mode Select. The TMS pin selects the next state in the TAP state
machine.
Input
Test Clock. This allows shifting of the data in, on the TMS and TDI pins. It
is a positive edge triggered clock with the TMS and TCK signals that
define the internal state of the device.
Input
Test Data In. This is the serial data input for the shift register.
Output
Test Data Output. This is the serial data output from the shift register.
Data is shifted out of the device on the negative edge of the TCK signal.
Input
Test Reset. The nTRST pin can be used to reset the test logic within the
EmbeddedICE logic.
Output
Returned Test Clock. Extra signal added to the JTAG port. Required for
designs based on ARM7TDMI-S processor core. Multi-ICE (Development
system from ARM) uses this signal to maintain synchronization with
targets having slow or widely varying clock frequency. For details refer to
"Multi-ICE System Design considerations Application Note 72 (ARM DAI
0072A)".
Rev. 01 — 15 August 2005
and the P1.26/RTCK pin. To have them come up as
SS
UM10139
Chapter 22: EmbeddedICE
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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