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- address 0xFFFF F034) bit description . . . . . .58
Table 55: Vector Address register (VICVectAddr - address
0xFFFF F030) bit description . . . . . . . . . . . . . .58
Table 56: Protection Enable register (VICProtection -
address 0xFFFF F020) bit description . . . . . . .58
Table 57: Connection of interrupt sources to the Vectored
Interrupt Controller (VIC) . . . . . . . . . . . . . . . . .59
Table 58: Pin description . . . . . . . . . . . . . . . . . . . . . . . . .69
Table 59: Pin connect block register map. . . . . . . . . . . . .75
Table 60: Pin function Select register 0 (PINSEL0 - address
0xE002 C000) bit description . . . . . . . . . . . . .76
Table 61: Pin function Select register 1 (PINSEL1 - address
0xE002 C004) bit description . . . . . . . . . . . . .78
Table 62: Pin function Select register 2 (PINSEL2 -
0xE002 C014) bit description . . . . . . . . . . . . .80
Table 63: Pin function select register bits . . . . . . . . . . . . .80
Table 64: GPIO pin description . . . . . . . . . . . . . . . . . . . .81
Table 65: GPIO register map (legacy VPB accessible
registers). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82
Table 66: GPIO register map (local bus accessible registers
- enhanced GPIO features). . . . . . . . . . . . . . . .83
Table 67: GPIO port 0 Direction register (IO0DIR - address
0xE002 8008) bit description . . . . . . . . . . . . . .83
Table 68: GPIO port 1 Direction register (IO1DIR - address
0xE002 8018) bit description . . . . . . . . . . . . . .84
Table 69: Fast GPIO port 0 Direction register (FIO0DIR -
address 0x3FFF C000) bit description . . . . . . .84
Table 70: Fast GPIO port 1 Direction register (FIO1DIR -
address 0x3FFF C020) bit description . . . . . . .84
Table 71: Fast GPIO port 0 Direction control byte and
half-word accessible register description . . . . .84
Table 72: Fast GPIO port 1 Direction control byte and
half-word accessible register description . . . . .85
Table 73: Fast GPIO port 0 Mask register (FIO0MASK -
address 0x3FFF C010) bit description . . . . . . .85
Table 74: Fast GPIO port 1 Mask register (FIO1MASK -
address 0x3FFF C030) bit description . . . . . . .85
Table 75: Fast GPIO port 0 Mask byte and half-word
accessible register description . . . . . . . . . . . . .86
Table 76: Fast GPIO port 1 Mask byte and half-word
accessible register description . . . . . . . . . . . . .86
Table 77: GPIO port 0 Pin value register (IO0PIN - address
0xE002 8000) bit description . . . . . . . . . . . . . .87
Table 78: GPIO port 1 Pin value register (IO1PIN - address
0xE002 8010) bit description . . . . . . . . . . . . . .87
Table 79: Fast GPIO port 0 Pin value register (FIO0PIN -
address 0x3FFF C014) bit description . . . . . . .87
Table 80: Fast GPIO port 1 Pin value register (FIO1PIN -
address 0x3FFF C034) bit description . . . . . . .87
Table 81: Fast GPIO port 0 Pin value byte and half-word
accessible register description . . . . . . . . . . . . .88
User manual
Table 82: Fast GPIO port 1 Pin value byte and half-word
accessible register description. . . . . . . . . . . . . 88
Table 83: GPIO port 0 output Set register (IO0SET -
address 0xE002 8004 bit description. . . . . . . . 89
Table 84: GPIO port 1 output Set register (IO1SET -
address 0xE002 8014) bit description . . . . . . . 89
Table 85: Fast GPIO port 0 output Set register (FIO0SET -
address 0x3FFF C018) bit description. . . . . . . 89
Table 86: Fast GPIO port 1 output Set register (FIO1SET -
address 0x3FFF C038) bit description. . . . . . . 89
Table 87: Fast GPIO port 0 output Set byte and half-word
accessible register description. . . . . . . . . . . . . 89
Table 88: Fast GPIO port 1 output Set byte and half-word
accessible register description. . . . . . . . . . . . . 90
Table 89: GPIO port 0 output Clear register 0 (IO0CLR -
address 0xE002 800C) bit description . . . . . . . 90
Table 90: GPIO port 1 output Clear register 1 (IO1CLR -
address 0xE002 801C) bit description . . . . . . . 90
Table 91: Fast GPIO port 0 output Clear register 0
(FIO0CLR - address 0x3FFF C01C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 92: Fast GPIO port 1 output Clear register 1
(FIO1CLR - address 0x3FFF C03C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 93: Fast GPIO port 0 output Clear byte and half-word
accessible register description. . . . . . . . . . . . . 91
Table 94: Fast GPIO port 1 output Clear byte and half-word
accessible register description. . . . . . . . . . . . . 91
Table 95: UART0 pin description . . . . . . . . . . . . . . . . . . . 95
Table 96: UART0 register map . . . . . . . . . . . . . . . . . . . . 96
Table 97: UART0 Receiver Buffer Register (U0RBR -
address 0xE000 C000, when DLAB = 0, Read
Only) bit description . . . . . . . . . . . . . . . . . . . . 97
Table 98: UART0 Transmit Holding Register (U0THR -
address 0xE000 C000, when DLAB = 0, Write
Only) bit description . . . . . . . . . . . . . . . . . . . . . 97
Table 99: UART0 Divisor Latch LSB register (U0DLL -
address 0xE000 C000, when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 100:UART0 Divisor Latch MSB register (U0DLM -
address 0xE000 C004, when DLAB = 1) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 101:UART0 Fractional Divider Register (U0FDR -
address 0xE000 C028) bit description . . . . . . . 98
Table 102:Baudrates available when using 20 MHz
peripheral clock (PCLK = 20 MHz). . . . . . . . . . 99
Table 103:UART0 Interrupt Enable Register (U0IER -
address 0xE000 C004, when DLAB = 0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Table 104:UART0 Interrupt Identification Register
(UOIIR - address 0xE000 C008, read only)
Rev. 01 — 15 August 2005
UM10139
Chapter 25: Supplementary information
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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