Architecture - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1
UART1 Rx
U1ACR Start
rate counter
16xbaud_rate
UART1 Rx
U1ACR Start
rate counter
16xbaud_rate
Fig 18. Autobaud Mode 0 and Mode 1 waveform

9.4 Architecture

The architecture of the UART0 is shown below in the block diagram.
The VPB interface provides a communications link between the CPU or host and the
UART0.
The UART0 receiver block, U0RX, monitors the serial input line, RXD0, for valid input. The
UART0 RX Shift Register (U0RSR) accepts valid characters via RXD0. After a valid
character is assembled in the U0RSR, it is passed to the UART0 RX Buffer Register FIFO
to await access by the CPU or host via the generic host interface.
User manual
'A' (0x41) or 'a' (0x61)
start bit0 bit1 bit2
Start bit
16 cycles
a) Mode 0 (Start bit and LSB are used for auto-baud)
'A' (0x41) or 'a' (0x61)
start bit0 bit1 bit2
Start bit
16 cycles
b) Mode 1 (only Start bit is used for auto-baud)
Rev. 01 — 15 August 2005
bit3 bit4 bit5 bit6
LSB of 'A' or 'a'
16 cycles
bit3 bit4 bit5 bit6
LSB of 'A' or 'a'
UM10139
Chapter 9: UART0
bit7 parity stop
bit7 parity stop
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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