Philips LPC214 Series User Manual page 341

Philips Semiconductors
Volume 1
Chapter 8: General Purpose Input/Output ports (GPIO)
8.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.3 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 81
8.4 Register description . . . . . . . . . . . . . . . . . . . . 81
8.4.1 GPIO port Direction register (IODIR, Port 0:
IO0DIR - 0xE002 8008 and Port 1: IO1DIR -
0xE002 8018; FIODIR, Port 0: FIO0DIR -
0x3FFF C000 and Port 1:FIO1DIR -
0x3FFF C020) . . . . . . . . . . . . . . . . . . . . . . . . 83
8.4.2 Fast GPIO port Mask register (FIOMASK, Port 0:
FIO0MASK - 0x3FFF C010 and Port
1:FIO1MASK - 0x3FFF C030) . . . . . . . . . . . . 85
8.4.3 GPIO port Pin value register (IOPIN, Port 0:
IO0PIN - 0xE002 8000 and Port 1: IO1PIN -
0xE002 8010; FIOPIN, Port 0: FIO0PIN -
0x3FFF C014 and Port 1: FIO1PIN -
0x3FFF C034) . . . . . . . . . . . . . . . . . . . . . . . . 86
Chapter 9: Universal Asynchronous Receiver/Transmitter 0 (UART0)
9.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 95
9.3 Register description . . . . . . . . . . . . . . . . . . . . 95
9.3.1 UART0 Receiver Buffer Register (U0RBR -
0xE000 C000, when DLAB = 0, Read Only). . 97
9.3.2 UART0 Transmit Holding Register (U0THR -
0xE000 C000, when DLAB = 0, Write Only). . 97
9.3.3 UART0 Divisor Latch Registers (U0DLL -
0xE000 C000 and U0DLM - 0xE000 C004, when
DLAB = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
9.3.4 UART0 Fractional Divider Register (U0FDR -
0xE000 C028). . . . . . . . . . . . . . . . . . . . . . . . . 98
9.3.5 UART0 baudrate calculation . . . . . . . . . . . . . . 99
9.3.6 UART0 Interrupt Enable Register (U0IER -
0xE000 C004, when DLAB = 0) . . . . . . . . . . 100
Chapter 10: Universal Asynchronous Receiver/Transmitter 1 (UART1)
10.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
10.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . 112
10.3 Register description . . . . . . . . . . . . . . . . . . . 113
10.3.1 UART1 Receiver Buffer Register (U1RBR -
0xE001 0000, when DLAB = 0 Read Only) . 115
User manual
8.4.4 GPIO port output Set register (IOSET, Port 0:
IO0SET - 0xE002 8004 and Port 1: IO1SET -
0xE002 8014; FIOSET, Port 0: FIO0SET -
0x3FFF C018 and Port 1: FIO1SET -
0x3FFF C038) . . . . . . . . . . . . . . . . . . . . . . . . 88
8.4.5 GPIO port output Clear register (IOCLR, Port 0:
IO0CLR - 0xE002 800C and Port 1: IO1CLR -
0xE002 801C; FIOCLR, Port 0: FIO0CLR -
0x3FFF C01C and Port 1: FIO1CLR -
0x3FFF C03C) . . . . . . . . . . . . . . . . . . . . . . . . 90
8.5 GPIO usage notes . . . . . . . . . . . . . . . . . . . . . . 92
8.5.1 Example 1: sequential accesses to IOSET and
IOCLR affecting the same GPIO pin/bit . . . . . 92
8.5.2 Example 2: an immediate output of 0s and 1s on
a GPIO port . . . . . . . . . . . . . . . . . . . . . . . . . . 92
8.5.3 Writing to IOSET/IOCLR .vs. IOPIN. . . . . . . . 93
8.5.4 Output signal frequency considerations when
using the legacy and enhanced GPIO registers .
93
9.3.7 UART0 Interrupt Identification Register (U0IIR -
0xE000 C008, Read Only) . . . . . . . . . . . . . . 101
9.3.8 UART0 FIFO Control Register (U0FCR -
0xE000 C008) . . . . . . . . . . . . . . . . . . . . . . . 103
9.3.9 UART0 Line Control Register (U0LCR -
0xE000 C00C) . . . . . . . . . . . . . . . . . . . . . . . 103
9.3.10 UART0 Line Status Register (U0LSR -
0xE000 C014, Read Only) . . . . . . . . . . . . . . 104
9.3.11 UART0 Scratch pad register (U0SCR -
0xE000 C01C) . . . . . . . . . . . . . . . . . . . . . . . 105
9.3.12 UART0 Auto-baud Control Register (U0ACR -
0xE000 C020) . . . . . . . . . . . . . . . . . . . . . . . 106
9.3.13 Auto-baud. . . . . . . . . . . . . . . . . . . . . . . . . . . 106
9.3.14 UART0 Transmit Enable Register (U0TER -
0xE000 C030) . . . . . . . . . . . . . . . . . . . . . . . 107
9.3.15 Auto-baud Modes. . . . . . . . . . . . . . . . . . . . . 108
9.4 Architecture . . . . . . . . . . . . . . . . . . . . . . . . . . 109
10.3.2 UART1 Transmitter Holding Register (U1THR -
0xE001 0000, when DLAB = 0 Write Only) . 115
10.3.3 UART1 Divisor Latch Registers 0 and 1 (U1DLL -
0xE001 0000 and U1DLM - 0xE001 0004, when
DLAB = 1) . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Rev. 01 - 15 August 2005
UM10139
Chapter 25: Supplementary information
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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