Pll Status Register (Pll0Stat - 0Xe01F C088, Pll1Stat - 0Xe01F C0A8); Pll Interrupt; Pll Modes - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1
3.8.4 PLL Status register (PLL0STAT - 0xE01F C088, PLL1STAT -
0xE01F C0A8)
The read-only PLLSTAT register provides the actual PLL parameters that are in effect at
the time it is read, as well as the PLL status. PLLSTAT may disagree with values found in
PLLCON and PLLCFG because changes to those registers do not take effect until a
proper PLL feed has occurred (see
0xE01F C08C, PLL1FEED - 0xE01F
Table 18:
Bit
4:0
6:5
7
8
9
10
15:11

3.8.5 PLL Interrupt

The PLOCK bit in the PLLSTAT register is connected to the interrupt controller. This allows
for software to turn on the PLL and continue with other functions without having to wait for
the PLL to achieve lock. When the interrupt occurs (PLOCK = 1), the PLL may be
connected, and the interrupt disabled. For details on how to enable and disable the PLL
interrupt, see
page 54
0xFFFF F014)" on page
PLL interrupt is available only in PLL0, i.e. the PLL that generates the CCLK. USB
dedicated PLL1 does not have this capability.

3.8.6 PLL Modes

The combinations of PLLE and PLLC are shown in
User manual
PLL Status register (PLL0STAT - address 0xE01F C088, PLL1STAT - address
0xE01F C0A8) bit description
Symbol Description
MSEL Read-back for the PLL Multiplier value. This is the value currently
used by the PLL.
PSEL Read-back for the PLL Divider value. This is the value currently
used by the PLL.
- Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
PLLE Read-back for the PLL Enable bit. When one, the PLL is currently
activated. When zero, the PLL is turned off. This bit is automatically
cleared when Power-down mode is activated.
PLLC Read-back for the PLL Connect bit. When PLLC and PLLE are both
one, the PLL is connected as the clock source for the
microcontroller. When either PLLC or PLLE is zero, the PLL is
bypassed and the oscillator clock is used directly by the
microcontroller. This bit is automatically cleared when Power-down
mode is activated.
PLOCK Reflects the PLL Lock status. When zero, the PLL is not locked.
When one, the PLL is locked onto the requested frequency.
- Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
Section 5.4.4 "Interrupt Enable register (VICIntEnable - 0xFFFF F010)" on
and Section 5.4.5 "Interrupt Enable Clear register (VICIntEnClear -
55.
Rev. 01 — 15 August 2005
Chapter 3: System Control Block
Section 3.8.7 "PLL Feed register (PLL0FEED -
C0AC)").
Table 19.
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10139
Reset
value
0
0
NA
0
0
0
NA
31