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Philips Semiconductors
Volume 1
14.12.5 Ending the packet transfer
The DMA engine will write back the DD with an updated status to the same memory
location from where it was read. The 'dma_buffer_start_addr', 'present_dma_count' and
the status bits field in the DD gets updated. Only words 2 and 3 are updated by hardware
in this mode.
A DD can have the following types of completion:
14.12.6 No_Packet DD
For IN transfers, it can happen that for a request, the system does not have any data to
send for a long time. The system can suppress this request by programming a no_packet
DD. This is done by setting the 'Maxpacketsize' and 'dma_buffer_length' in the DD control
field to 0. No packets will be sent to the host in response to the no_packet DD.
14.13 Concatenated transfer (ATLE) mode operation
Some host drivers like 'NDIS' (Network Driver Interface Standard) are capable of
concatenating small transfers (delta transfers) to form a single large transfer. The device
hardware should be able to break up this single transfer back into delta transfers and
transfer them to different DMA buffers. This is achieved in the ATLE mode operation. This
is applicable only for Bulk endpoints.
In ATLE mode, the Host driver can concatenate various transfer lengths, which
correspond to different DMA descriptors on Device side. And these transfers have to be
done on USB without breaking the packet. This is the primary difference between the
Normal Mode of DMA operation and ATLE mode, wherein one DMA transfer length ends
with either a full USB packet or a short packet and next DMA transfer length starts with a
new USB packet in Normal mode, but these two transfers may be concatenated in the last
USB packet of the first DMA transfer in ATLE mode.
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User manual
Normal completion - If the current packet is fully transferred and the 'dma_count' field
equals the 'dma_buffer_length' defined in the descriptor, the DD has a normal
completion. The DD will be written back to memory with 'DD_retired' bit set.
END_OF_TRANSFER interrupt is raised for this endpoint. DD_Status bits are updated
for 'normal_completion' code.
Transfer end completion - If the current packet is fully transferred and its size is less
than the 'max_packet_size' defined in the descriptor, and the end of the buffer is still not
reached the transfer end completion occurs. The DD will be written back to the memory
with 'DD_retired' bit set and DD_Status bits showing 'data under run' completion code.
Also, the 'END_OF_TRANSFER' interrupt for this endpoint is raised.
Error completion - If the current packet is partially transferred i.e. end of the DMA
buffer is reached in the middle of the packet transfer, an error situation occurs. The DD
is written back with DD_status 'data over run' and 'DD_retired' bit is set. The DMA
engine will raise the end of transfer interrupt and resets the corresponding bit for this
endpoint in the 'DMA_ENABLE' register. This packet will be retransmitted to the
memory fully when DMA_ENABLE bit is set again.
Rev. 01 — 15 August 2005
UM10139
Chapter 14: USB Device Controller
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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