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Philips Semiconductors
Volume 1
14.11 DMA operation
14.11.1 Triggering the DMA engine
An endpoint will raise a DMA request when the slave mode transfer is disabled by setting
the corresponding bit in Endpoint Interrupt Enable register to 0
The DMA transfer for an OUT endpoint is triggered when it receives a packet without any
errors (i.e., the buffer is full) and the DMA_ENABLE
Status register (USBEpDMASt - 0xE009
Transfer for an IN endpoint is triggered when the host requests for a packet of data and
the DMA_ENABLE bit is set for this endpoint.
In DMA mode, the bits corresponding to Interrupt on NAK for Bulk OUT and Interrupt OUT
endpoints (bit INAK_BO and INAK_IO) in Set Mode register
(Command: 0xF3, Data: write 1
14.11.2 Arbitration between endpoints
If more than one endpoint is requests for data transfer at the same time the endpoint with
lower physical endpoint number value gets the priority.
14.12 Non Isochronous Endpoints - Normal Mode operation
14.12.1 Setting up DMA transfer
The software prepares the DDs for the physical endpoints that need DMA transfer. These
DDs are present in the USB RAM. Also, the start address of the first DD is programmed
into the DDP location for the corresponding endpoint. The software will then set the
DMA_ENABLE bit for this endpoint in the EP DMA Status register
'dma_mode' bits in the descriptor has to be set to '00' for normal mode operation. It should
also initialize all the bits in the DD as given in the table.
14.12.2 Finding DMA Descriptor
When there is a trigger for a DMA transfer for an endpoint, DMA engine will first determine
whether a new descriptor has to the fetched or not. A new descriptor need not have to be
fetched if the last transfer was also made for the same endpoint and the DD is not yet in
the 'retired' state. A flag called 'DMA_PROCEED' is used to identify this (see
14.12.4 "Optimizing Descriptor Fetch" on page
If a new descriptor has to be read, the DMA engine will calculate the location of the DDP
for this endpoint and will fetch the start address of DD from this location. A DD start
address at location zero is considered invalid. In this case a 'new_dd_request' interrupt is
raised. All other word boundaries are valid.
At any point of time if the DD is to be fetched, the status of DD (word 3) is read first and
the status of the 'DD_retired' bit is checked. If this is not set, DDP points to a valid DD. If
the 'DD_retired' bit is set, the DMA engine will read the 'control' field (word 1) of the DD.
If the bit 'next_DD_valid' bit' is set, the DMA engine will fetch the 'next_dd_pointer' field
(word 0) of the DD and load it to the DDP. The new DDP is written to the UDCA area.
9397 750 XXXXX
User manual
0084)") bit is set for this endpoint.
byte)") should be reset to 0.
Rev. 01 — 15 August 2005
UM10139
Chapter 14: USB Device Controller
(Section
(Section 14.8.15 "USB EP DMA
(Section 14.9.3 "Set Mode
(Section
235).
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
14.7.8).
14.8.15).The
Section
234
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