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Philips Semiconductors
Volume 1
Table 8:
Name
INTWAKE
EXTMODE
EXTPOLAR
[1]
3.5.2 External Interrupt Flag register (EXTINT - 0xE01F C140)
When a pin is selected for its external interrupt function, the level or edge on that pin
(selected by its bits in the EXTPOLAR and EXTMODE registers) will set its interrupt flag in
this register. This asserts the corresponding interrupt request to the VIC, which will cause
an interrupt if interrupts from the pin are enabled.
Writing ones to bits EINT0 through EINT3 in EXTINT register clears the corresponding
bits. In level-sensitive mode this action is efficacious only when the pin is in its inactive
state.
Once a bit from EINT0 to EINT3 is set and an appropriate code starts to execute (handling
wakeup and/or external interrupt), this bit in EXTINT register must be cleared. Otherwise
the event that was just triggered by activity on the EINT pin will not be recognized in the
future.
Important: whenever a change of external interrupt operating mode (i.e. active
level/edge) is performed (including the initialization of an external interrupt), the
corresponding bit in the EXTINT register must be cleared! For details see
3.5.4 "External Interrupt Mode register (EXTMODE - 0xE01F C148)"
"External Interrupt Polarity register (EXTPOLAR - 0xE01F
For example, if a system wakes up from power-down using a low level on external
interrupt 0 pin, its post-wakeup code must reset the EINT0 bit in order to allow future entry
into the power-down mode. If the EINT0 bit is left set to 1, subsequent attempt(s) to invoke
power-down mode will fail. The same goes for external interrupt handling.
More details on power-down mode will be discussed in the following chapters.
User manual
External interrupt registers
Description
The Interrupt Wakeup Register contains four
enable bits that control whether each external
interrupt will cause the processor to wake up
from Power-down mode. See
The External Interrupt Mode Register controls
whether each pin is edge- or level sensitive.
The External Interrupt Polarity Register controls
which level or edge on each pin will cause an
interrupt.
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Rev. 01 — 15 August 2005
Chapter 3: System Control Block
Access Reset
R/W
Table
10.
R/W
R/W
C14C)".
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10139
Address
[1]
value
0
0xE01F C144
0
0xE01F C148
0
0xE01F C14C
Section
and
Section 3.5.5
21
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