Table of Contents
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Volume 1
Table 151:Slave Transmitter mode . . . . . . . . . . . . . . . . .158
Table 152:Miscellaneous States . . . . . . . . . . . . . . . . . . .160
Table 153:SPI data to clock phase relationship. . . . . . . .172
Table 154:SPI pin description . . . . . . . . . . . . . . . . . . . . .175
Table 155:SPI register map . . . . . . . . . . . . . . . . . . . . . . .176
Table 156:SPI Control Register (S0SPCR - address
0xE002 0000) bit description . . . . . . . . . . . . .176
Table 157:SPI Status Register (S0SPSR - address
0xE002 0004) bit description . . . . . . . . . . . . .177
Table 158:SPI Data Register (S0SPDR - address
0xE002 0008) bit description . . . . . . . . . . . . .178
Table 159:SPI Clock Counter Register (S0SPCCR - address
0xE002 000C) bit description . . . . . . . . . . . . .178
Table 160:SPI Interrupt register (S0SPINT - address
0xE002 001C) bit description . . . . . . . . . . . . .179
Table 161:SSP pin descriptions . . . . . . . . . . . . . . . . . . .180
Table 162:SSP register map . . . . . . . . . . . . . . . . . . . . . .189
Table 163:SSP Control Register 0 (SSPCR0 - address
0xE006 8000) bit description . . . . . . . . . . . . .189
Table 164:SSP Control Register 1 (SSPCR1 - address
0xE006 8004) bit description . . . . . . . . . . . . .190
Table 165:SSP Data Register (SSPDR - address
0xE006 8008) bit description . . . . . . . . . . . . .191
Table 166:SSP Status Register (SSPDR - address
0xE006 800C) bit description . . . . . . . . . . . . .191
Table 167:SSP Clock Prescale Register (SSPCPSR -
address 0xE006 8010) bit description . . . . . .191
Table 168:SSP Interrupt Mask Set/Clear register (SSPIMSC
- address 0xE006 8014) bit description . . . . .192
Table 169:SSP Raw Interrupt Status register (SSPRIS -
address 0xE006 8018) bit description . . . . . .192
Table 170:SSP Masked Interrupt Status register (SSPMIS
-address 0xE006 801C) bit description . . . . .193
Table 171:SSP interrupt Clear Register (SSPICR - address
0xE006 8020) bit description . . . . . . . . . . . . .193
Table 172:USB related acronyms, abbreviations and
definitions used in this chapter . . . . . . . . . . . .194
Table 173:Pre-Fixed Endpoint Configuration. . . . . . . . . .195
Table 174:USB device register map . . . . . . . . . . . . . . . .199
Table 175:USB Interrupt Status register (USBIntSt - address
0xE01F C1C0) bit description. . . . . . . . . . . . .200
Table 176:USB Device Interrupt Status register
(USBDevIntSt - address 0xE009 0000) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .201
Table 177:USB Device Interrupt Status register
(USBDevIntSt - address 0xE009 0000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .201
Table 178:USB Device Interrupt Enable register
(USBDevIntEn - address 0xE009 0004) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . .202
Table 179:USB Device Interrupt Enable register
User manual
(USBDevIntEn - address 0xE009 0004) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 180:USB Device Interrupt Clear register
(USBDevIntClr - address 0xE009 0008) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 202
Table 181:USB Device Interrupt Clear register
(USBDevIntClr - address 0xE009 0008) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 203
Table 182:USB Device Interrupt Set register (USBDevIntSet
- address 0xE009 000C) bit allocation . . . . . 203
Table 183:USB Device Interrupt Set register (USBDevIntSet
- address 0xE009 000C) bit description. . . . . 203
Table 184:USB Device Interrupt Priority register
(USBDevIntPri - address 0xE009 002C) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 185:USB Endpoint Interrupt Status register
(USBEpIntSt - address 0xE009 0030) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 186:USB Endpoint Interrupt Status register
(USBEpIntSt - address 0xE009 0030) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 204
Table 187:USB Endpoint Interrupt Enable register
(USBEpIntEn - address 0xE009 0034) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
Table 188:USB Endpoint Interrupt Enable register
(USBEpIntEn - address 0xE009 0034) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 189:USB Endpoint Interrupt Clear register
(USBEpIntClr - address 0xE009 0038) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 190:USB Endpoint Interrupt Clear register
(USBEpIntClr - address 0xE009 0038) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 206
Table 191:USB Endpoint Interrupt Set register (USBEpIntSet
- address 0xE009 003C) bit allocation . . . . . 207
Table 192:USB Endpoint Interrupt Set register (USBEpIntSet
- address 0xE009 003C) bit description. . . . . 207
Table 193:USB Endpoint Interrupt Priority register
(USBEpIntPri - address 0xE009 0040) bit
allocation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 207
Table 194:USB Endpoint Interrupt Priority register
(USBEpIntPri - address 0xE009 0040) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 208
Table 195:USB Realize Endpoint register (USBReEp -
address 0xE009 0044) bit allocation . . . . . . . 208
Table 196:USB Realize Endpoint register (USBReEp -
address 0xE009 0044) bit description . . . . . . 208
Table 197:USB Endpoint Index register (USBEpIn - address
0xE009 0048) bit description . . . . . . . . . . . . . 210
Table 198:USB MaxPacketSize register (USBMaxPSize -
address 0xE009 004C) bit description . . . . . . 210
Rev. 01 — 15 August 2005
UM10139
Chapter 25: Supplementary information
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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