Table of Contents
Advertisement
Philips Semiconductors
Volume 1
Table 173: Pre-Fixed Endpoint Configuration
Logical
Physical
endpoint
endpoint
7
14
7
15
8
16
8
17
9
18
9
19
10
20
10
21
11
22
11
23
12
24
12
25
13
26
13
27
14
28
14
29
15
30
15
31
14.4 Architecture
The architecture of the USB device controller is shown below in the block diagram.
DMA
Interface
(AHB master)
Register
Interface
(AHB slave)
Fig 50. USB Device Controller Block Diagram
9397 750 XXXXX
User manual
Endpoint type
Interrupt
Interrupt
Bulk
Bulk
Isochronous
Isochronous
Interrupt
Interrupt
Bulk
Bulk
Isochronous
Isochronous
Interrupt
Interrupt
Bulk
Bulk
Bulk
Bulk
Bus
Master
Interface
Register
Interface
USB Device
Block
Rev. 01 — 15 August 2005
Chapter 14: USB Device Controller
Direction
Packet size (bytes)
Out
1 to 64
In
1 to 64
Out
8, 16, 32, 64
In
8, 16, 32, 64
Out
1 to 1023
In
1 to 1023
Out
1 to 64
In
1 to 64
Out
8, 16, 32, 64
In
8, 16, 32, 64
Out
1 to 1023
In
1 to 1023
Out
1 to 64
In
1 to 64
Out
8, 16, 32, 64
In
8, 16, 32, 64
Out
8, 16, 32, 64
In
8, 16, 32, 64
DMA
Engine
EP_RAM
Serial
Access
Interface
Control
Engine
EP_RAM
(2K)
UM10139
Double buffer
No
No
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
No
No
Yes
Yes
Yes
Yes
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
196
Advertisement
Table of Contents
