Architecture - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1

15.7 Architecture

The block diagram for TIMER/COUNTER0 and TIMER/COUNTER1 is shown in
Figure
User manual
58.
MATCH REGISTER 0
MATCH REGISTER 1
MATCH REGISTER 2
MATCH REGISTER 3
MATCH CONTROL REGISTER
EXTERNAL MATCH REGISTER
INTRRUPT REGISTER
MAT[3:0]
INTERRUPT
CAP[3:0]
STOP ON MATCH
RESET ON MATCH
LOAD[3:0]
CAPTURE CONTROL REGISTER
CAPTURE REGISTER 0
CAPTURE REGISTER 1
CAPTURE REGISTER 2
CAPTURE REGISTER 3*
TIMER CONTROL REGISTER
* Note: that the capture register 3 cannot be used on TIMER0
Fig 58. Timer block diagram
Rev. 01 — 15 August 2005
CONTROL
RESET ENABLE
UM10139
Chapter 15: TIMER0 and TIMER1
=
=
=
=
CSN
TIMER COUNTER
CE
TCI
PRESCALE COUNTER
MAXVAL
PRESCALE REGISTER
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
PCLK
252