Philips LPC214 Series User Manual page 335

Philips Semiconductors
Volume 1
Table 199:USB Receive Data register (USBRxData -
address 0xE009 0018) bit description . . . . . .211
Table 200:USB Receive Packet Length register (USBRxPlen
- address 0xE009 0020) bit description . . . . .211
Table 201:USB Transmit Data register (USBTxData -
address 0xE009 001C) bit description . . . . . .211
Table 202:USB Transmit Packet Length register
(USBTxPLen - address 0xE009 0024) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .212
Table 203:USB Control register (USBCtrl - address
0xE009 0028) bit description . . . . . . . . . . . . .212
Table 204:USB Command Code register (USBCmdCode -
address 0xE009 0010) bit description . . . . . .213
Table 205:USB Command Data register (USBCmdData -
address 0xE009 0014) bit description . . . . . .214
Table 206:USB DMA Request Status register (USBDMARSt
- address 0xE009 0050) bit allocation . . . . . .214
Table 207:USB DMA Request Status register (USBDMARSt
- address 0xE009 0050) bit description . . . . .214
Table 208:USB DMA Request Clear register (USBDMARClr
- address 0xE009 0054) bit description . . . . .215
Table 209:USB DMA Request Set register (USBDMARSet -
address 0xE009 0058) bit description . . . . . .215
Table 210:USB UDCA Head register (USBUDCAH - address
0xE009 0080) bit description . . . . . . . . . . . . .216
Table 211:USB EP DMA Status register (USBEpDMASt -
address 0xE009 0084) bit description . . . . . .217
Table 212:USB EP DMA Enable register (USBEpDMAEn -
address 0xE009 0088) bit description . . . . . .217
Table 213:USB EP DMA Disable register (USBEpDMADis -
address 0xE009 008C) bit description . . . . . .218
Table 214:USB DMA Interrupt Status register
(USBDMAIntSt - address 0xE009 0090) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .218
Table 215:USB DMA Interrupt Enable register
(USBDMAIntEn - address 0xE009 0094) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .219
Table 216:USB End of Transfer Interrupt Status register
(USBEoTIntSt - address 0xE009 00A0s) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .219
Table 217:USB End of Transfer Interrupt Clear register
(USBEoTIntClr - address 0xE009 00A4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .219
Table 218:USB End of Transfer Interrupt Set register
(USBEoTIntSet - address 0xE009 00A8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .220
Table 219:USB New DD Request Interrupt Status register
(USBNDDRIntSt - address 0xE009 00AC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .220
Table 220:USB New DD Request Interrupt Clear register
(USBNDDRIntClr - address 0xE009 00B0) bit
User manual
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 220
Table 221:USB New DD Request Interrupt Set register
(USBNDDRIntSet - address 0xE009 00B4) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 222:USB System Error Interrupt Status register
(USBSysErrIntSt - address 0xE009 00B8) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 223:USB System Error Interrupt Clear register
(USBSysErrIntClr - address 0xE009 00BC) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 221
Table 224:USB System Error Interrupt Set register
(USBSysErrIntSet - address 0xE009 00C0) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . . 222
Table 225:Protocol engine command code table . . . . . . 222
Table 226:Device Set Address Register bit description . 223
Table 227:Configure Device Register bit description . . . 224
Table 228:Set Mode Register bit description . . . . . . . . . 224
Table 229:Set Device Status Register bit description . . . 225
Table 230:Get Error Code Register bit description . . . . . 227
Table 231:Read Error Status Register bit description. . . 227
Table 232:Select Endpoint Register bit description . . . . 228
Table 233:Set Endpoint Status Register bit description . 229
Table 234:Clear Buffer Register bit description . . . . . . . 230
Table 235:DMA descriptor . . . . . . . . . . . . . . . . . . . . . . . 231
Table 236:Timer/Counter pin description . . . . . . . . . . . . 243
Table 237:TIMER/COUNTER0 and TIMER/COUNTER1
register map . . . . . . . . . . . . . . . . . . . . . . . . . . 244
Table 238:Interrupt Register (IR, TIMER0: T0IR - address
0xE000 4000 and TIMER1: T1IR - address
0xE000 8000) bit description . . . . . . . . . . . . . 245
Table 239:Timer Control Register (TCR, TIMER0: T0TCR -
address 0xE000 4004 and TIMER1: T1TCR -
address 0xE000 8004) bit description . . . . . . 246
Table 240:Count Control Register (CTCR,
TIMER0: T0CTCR - address 0xE000 4070 and
TIMER1: T1TCR - address 0xE000 8070)
bit description. . . . . . . . . . . . . . . . . . . . . . . . . 246
Table 241:Match Control Register (MCR, TIMER0: T0MCR -
address 0xE000 4014 and TIMER1: T1MCR -
address 0xE000 8014) bit description . . . . . . 248
Table 242:Capture Control Register (CCR, TIMER0: T0CCR
- address 0xE000 4028 and TIMER1: T1CCR -
address 0xE000 8028) bit description . . . . . . 249
Table 243:External Match Register (EMR, TIMER0: T0EMR
- address 0xE000 403C and TIMER1: T1EMR -
address0xE000 803C) bit description . . . . . . 250
Table 244:External match control . . . . . . . . . . . . . . . . . . 251
Table 245:Set and reset inputs for PWM Flip-Flops . . . . 256
Table 246:Pin summary . . . . . . . . . . . . . . . . . . . . . . . . . 257
Table 247:Pulse Width Modulator (PWM) register map . 258
Table 248:PWM Interrupt Register (PWMIR - address
Rev. 01 — 15 August 2005
UM10139
Chapter 25: Supplementary information
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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