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Philips Semiconductors
Volume 1
For an external interrupt pin to be a source that would wake up the microcontroller from
Power-down mode, it is also necessary to clear the corresponding bit in the External
Interrupt Flag register
Table 10:
Bit
0
1
2
3
4
5
13:4
14
15
3.5.4 External Interrupt Mode register (EXTMODE - 0xE01F C148)
The bits in this register select whether each EINT pin is level- or edge-sensitive. Only pins
that are selected for the EINT function (see chapter Pin Connect Block on page 75) and
enabled via the VICIntEnable register
(VICIntEnable - 0xFFFF F010)" on page
Interrupt function (though of course pins selected for other functions may cause interrupts
from those functions).
Note: Software should only change a bit in this register when its interrupt is
disabled in the VICIntEnable register, and should write the corresponding 1 to the
EXTINT register before enabling (initializing) or re-enabling the interrupt, to clear
the EXTINT bit that could be set by changing the mode.
Table 11:
Bit
0
1
User manual
(Section 3.5.2 on page
Interrupt Wakeup register (INTWAKE - address 0xE01F C144) bit description
Symbol
Description
EXTWAKE0
When one, assertion of EINT0 will wake up the processor from
Power-down mode.
EXTWAKE1
When one, assertion of EINT1 will wake up the processor from
Power-down mode.
EXTWAKE2
When one, assertion of EINT2 will wake up the processor from
Power-down mode.
EXTWAKE3
When one, assertion of EINT3 will wake up the processor from
Power-down mode.
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
USBWAKE
When one, activity of the USB bus (USB_need_clock = 1) will
wake up the processor from Power-down mode. Any change of
state on the USB data pins will cause a wakeup when this bit is
set. For details on the relationship of USB to Power-down mode
and wakeup, see
(USBIntSt - 0xE01F C1C0)" on page 200
"PLL and Power-down mode" on page
-
Reserved, user software should not write ones to reserved bits.
The value read from a reserved bit is not defined.
BODWAKE
When one, a BOD interrupt will wake up the processor from
Power-down mode.
RTCWAKE
When one, assertion of an RTC interrupt will wake up the
processor from Power-down mode.
External Interrupt Mode register (EXTMODE - address 0xE01F C148) bit
description
Symbol
Value
Description
EXTMODE0 0
Level-sensitivity is selected for EINT0.
1
EINT0 is edge sensitive.
EXTMODE1 0
Level-sensitivity is selected for EINT1.
Rev. 01 — 15 August 2005
Chapter 3: System Control Block
21).
Section 14.7.1 "USB Interrupt Status register
and
32.
(Section 5.4.4 "Interrupt Enable register
54) can cause interrupts from the External
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10139
Reset
value
0
0
0
0
NA
0
Section 3.8.8
NA
0
0
Reset
value
0
0
23
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