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Philips Semiconductors
Volume 1
14.10.10 Packet_valid
This bit indicates whether the last packet transferred to the memory is received with errors
or not. This bit will be set if the packet is valid, i.e., it was received without errors. Since
non-isochronous endpoint will not generate DMA request for packet with errors, this field
will not make much sense to them as it will be set for all packets transferred. But for
isochronous endpoints this information is useful. See
Endpoint Operation" on page 240
14.10.11 LS_byte_extracted
Applicable only in the ATLE mode. This bit set indicates that the Least Significant Byte
(LSB) of the transfer length has been already extracted. The extracted size will be
reflected in the 'dma_buffer_length' field in the bits 23:16.
14.10.12 MS_byte_extracted
Applicable only in the ATLE mode. This bit set indicates that the Most Significant Byte
(MSB) of the transfer size has been already extracted. The size extracted will be reflected
in the 'dma_buffer_length' field at 31:24. Extraction stops when 'LS_Byte_extracted' and
'MS_byte_extracted' fields are set.
14.10.13 Present_DMA_count
The number of bytes transferred by the DMA engine at any point of time. This is updated
packet-wise by the DMA engine when it updates the descriptor. In case of the Isochronous
endpoints the Present_DMA_count is specified in terms of number of packets transferred.
14.10.14 Message_length_position
This applies only in the ATLE mode. This field gives the offset of the message length
position embedded in the packet. This is applicable only for OUT endpoints. Offset 0
indicates that the message length starts from the first byte of the packet onwards.
14.10.15 Isochronous_packetsize_memory_address
The memory buffer address where the packet size information along with the frame
number has to be transferred or fetched. See
endpoints only.
9397 750 XXXXX
User manual
•
Normal completion - The DD is retired because the end of the buffer is reached and
there were no errors. DD_retired bit also is set.
•
Data under run - Before reaching the end of the buffer, transfer is terminated
because a short packet is received. DD_retired bit also is set.
•
Data over run - End of the DMA buffer is reached in the middle of a packet transfer.
This is an error situation. DD_retired bit will be set. The DMA count will show the value
of DMA buffer length. The packet has to be re-transmitted from the FIFO.
DMA_ENABLE bit is reset.
•
System error - Transfer is terminated because of an error in the system bus.
DD_retired bit is not set in this case. DMA_ENABLE bit is reset. Since system error
can happen while updating the DD, the DD fields in the USB RAM may not be very
reliable.
Rev. 01 — 15 August 2005
Chapter 14: USB Device Controller
Section 14.14 "Isochronous
for isochronous endpoint operation.
Figure
55. This is applicable to isochronous
UM10139
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
233
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