Table of Contents
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Philips Semiconductors
Volume 1
25.4 Tables
Table 1:
LPC2141/2/4/6/8 device information. . . . . . . . . .4
Table 2:
VPB peripheries and base addresses . . . . . . .10
Table 3:
ARM exception vector locations . . . . . . . . . . . .12
Table 4:
LPC2141/2/4/6/8 memory mapping modes . . .12
Table 5:
Pin summary. . . . . . . . . . . . . . . . . . . . . . . . . . .16
Table 6:
Summary of system control registers . . . . . . . .17
Table 7:
Recommended values for C
mode (crystal and external components
parameters) . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Table 8:
External interrupt registers . . . . . . . . . . . . . . . .20
Table 9:
External Interrupt Flag register (EXTINT - address
0xE01F C140) bit description . . . . . . . . . . . . . .22
Table 10: Interrupt Wakeup register (INTWAKE - address
0xE01F C144) bit description . . . . . . . . . . . . . .23
Table 11: External Interrupt Mode register (EXTMODE -
address 0xE01F C148) bit description . . . . . . .23
Table 12: External Interrupt Polarity register (EXTPOLAR -
address 0xE01F C14C) bit description. . . . . . .24
Table 13: System Control and Status flags register (SCS -
address 0xE01F C1A0) bit description . . . . . . .26
Table 14: Memory Mapping control register (MEMMAP -
address 0xE01F C040) bit description . . . . . . .27
Table 15: PLL registers . . . . . . . . . . . . . . . . . . . . . . . . . .28
Table 16: PLL Control register (PLL0CON - address
0xE01F C080, PLL1CON - address
0xE01F C0A0) bit description. . . . . . . . . . . . . .30
Table 17: PLL Configuration register (PLL0CFG - address
0xE01F C084, PLL1CFG - address
0xE01F C0A4) bit description. . . . . . . . . . . . . .30
Table 18: PLL Status register (PLL0STAT - address
0xE01F C088, PLL1STAT - address
0xE01F C0A8) bit description. . . . . . . . . . . . . .31
Table 19: PLL Control bit combinations . . . . . . . . . . . . . .32
Table 20: PLL Feed register (PLL0FEED - address
0xE01F C08C, PLL1FEED - address
0xE01F C0AC) bit description . . . . . . . . . . . . .32
Table 21: Elements determining PLL's frequency. . . . . . .33
Table 22: PLL Divider values . . . . . . . . . . . . . . . . . . . . . .34
Table 23: PLL Multiplier values. . . . . . . . . . . . . . . . . . . . .34
Table 24: Power control registers . . . . . . . . . . . . . . . . . . .35
Table 25: Power Control register (PCON - address
0xE01F COCO) bit description . . . . . . . . . . . . .36
Table 26: Power Control for Peripherals register (PCONP -
address 0xE01F C0C4) bit description. . . . . . .37
Table 27: Reset Source identification Register (RSIR -
address 0xE01F C180) bit description . . . . . . .39
Table 28: VPB divider register map . . . . . . . . . . . . . . . . .40
Table 29: VPB Divider register (VPBDIV - address
User manual
Table 30: MAM Responses to program accesses of various
Table 31: MAM responses to data and DMA accesses of
Table 32: Summary of MAM registers . . . . . . . . . . . . . . . 48
in oscillation
Table 33: MAM Control Register (MAMCR - address
X1/X2
Table 34: MAM Timing register (MAMTIM - address
Table 35: VIC register map . . . . . . . . . . . . . . . . . . . . . . . 51
Table 36: Software Interrupt register (VICSoftInt - address
Table 37: Software Interrupt register (VICSoftInt - address
Table 38: Software Interrupt Clear register (VICSoftIntClear
Table 39: Software Interrupt Clear register (VICSoftIntClear
Table 40: Raw Interrupt status register (VICRawIntr -
Table 41: Raw Interrupt status register (VICRawIntr -
Table 42: Interrupt Enable register (VICIntEnable - address
Table 43: Interrupt Enable register (VICIntEnable - address
Table 44: Software Interrupt Clear register (VICIntEnClear -
Table 45: Software Interrupt Clear register (VICIntEnClear -
Table 46: Interrupt Select register (VICIntSelect - address
Table 47: Interrupt Select register (VICIntSelect - address
Table 48: IRQ Status register (VICIRQStatus - address
Table 49: IRQ Status register (VICIRQStatus - address
Table 50: FIQ Status register (VICFIQStatus - address
Table 51: FIQ Status register (VICFIQStatus - address
Table 52: Vector Control registers 0-15 (VICVectCntl0-15 -
Table 53: Vector Address registers (VICVectAddr0-15 -
Table 54: Default Vector Address register (VICDefVectAddr
Rev. 01 — 15 August 2005
Chapter 25: Supplementary information
0xE01F C100) bit description. . . . . . . . . . . . . . 41
types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
various types . . . . . . . . . . . . . . . . . . . . . . . . . . 47
0xE01F C000) bit description. . . . . . . . . . . . . . 48
0xE01F C004) bit description. . . . . . . . . . . . . . 48
0xFFFF F018) bit allocation . . . . . . . . . . . . . . 52
0xFFFF F018) bit description. . . . . . . . . . . . . . 53
- address 0xFFFF F01C) bit allocation . . . . . . 53
- address 0xFFFF F01C) bit description . . . . . 53
address 0xFFFF F008) bit allocation . . . . . . . 54
address 0xFFFF F008) bit description . . . . . . . 54
0xFFFF F010) bit allocation . . . . . . . . . . . . . . 54
0xFFFF F010) bit description. . . . . . . . . . . . . . 55
address 0xFFFF F014) bit allocation . . . . . . . 55
address 0xFFFF F014) bit description . . . . . . . 55
0xFFFF F00C) bit allocation . . . . . . . . . . . . . . 55
0xFFFF F00C) bit description . . . . . . . . . . . . . 56
0xFFFF F000) bit allocation . . . . . . . . . . . . . . 56
0xFFFF F000) bit description. . . . . . . . . . . . . . 56
0xFFFF F004) bit allocation . . . . . . . . . . . . . . 57
0xFFFF F004) bit description. . . . . . . . . . . . . . 57
0xFFFF F200-23C) bit description . . . . . . . . . . 57
addresses 0xFFFF F100-13C) bit description . 58
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10139
continued >>
331
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