Usb Dma Request Set Register (Usbdmarset - 0Xe009 0058) - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1
Table 208: USB DMA Request Clear register (USBDMARClr - address 0xE009 0054) bit description
Bit Symbol Value
0 EP0 0
1 EP1 0
31:2 EPxx
0
1
The software should not clear the DMA request clear bit while the DMA operation is in
progress. But if at all the clearing happens, the behavior of DMA engine will depend on at
what time the clearing is done. There can be more than one DMA requests pending at any
given time. The DMA engine processes these requests serially (i.e starting from EP2 to
EP31). If the DMA request for a particular endpoint is cleared before DMA operation has
started for that request, then the DMA engine will never know about the request and no
DMA operation on that endpoint will be done (till the next request appears). On the other
hand, if the DMA request for a particular endpoint is cleared after the DMA operation
corresponding to that request has begun, it does not matter even if the request is cleared,
since the DMA engine has registered the endpoint number internally and will not sample
the same request before finishing the current DMA operation.

14.8.13 USB DMA Request Set register (USBDMARSet - 0xE009 0058)

Writing 1 into the register will set the corresponding interrupt from the DMA request
register. Writing 0 will not have any effect. The USBDMARSet is a write only register.
The USBDMARSet bit allocation is identical to the USBDMARSt register
Table 209: USB DMA Request Set register (USBDMARSet - address 0xE009 0058) bit
Bit
0
1
31:2 EPxx
The DMA Request Set register is normally used for the test purpose. It is also useful in the
normal operation mode to avoid a "lock" situation if the DMA is programmed after that the
USB packets are already received. Normally the arrival of a packet generates an interrupt
when it is completely received. This interrupt is used by the DMA to start working. This
works fine as long as the DMA is programmed before the arrival of the packet (2 packets -
if double buffered). If the DMA is programmed "too late", the interrupts were already
generated in slave mode (but not handled because the intention was to use the DMA) and
when the DMA is programmed no interrupts are generated to "activate" it. In this case the
usage of the DMA Request Set register is useful to manually start the DMA transfer.
9397 750 XXXXX
User manual
Description
Control endpoint OUT (DMA cannot be enabled for this endpoint and the
EP0 bit must be 0).
Control endpoint IN (DMA cannot be enabled for this endpoint and the EP1
bit must be 0).
Clear the endpoint xx (2
No effect.
Clear the corresponding interrupt from the DMA request register.
description
Symbol Value Description
EP0 0 Control endpoint OUT (DMA cannot be enabled for this endpoint
and the EP0 bit must be 0).
EP1 0 Control endpoint IN (DMA cannot be enabled for this endpoint and
the EP1 bit must be 0).
Set the endpoint xx (2
0 No effect.
1 Set the corresponding interrupt from the DMA request register.
Rev. 01 — 15 August 2005
Chapter 14: USB Device Controller
≤ ≤
xx 31) DMA request.
≤ ≤
xx 31) DMA request interrupt.
UM10139
Reset value
0
0
0
(Table 206).
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset
value
0
0
0
215