Fast Gpio Port Mask Register (Fiomask, Port 0: Fio0Mask - 0X3Fff C010 And Port 1:Fio1Mask - 0X3Fff C030) - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1
Table 72: Fast GPIO port 1 Direction control byte and half-word accessible register description
Register Register
name length (bits)
& access
FIO1DIR0 8 (byte)
FIO1DIR1 8 (byte)
FIO1DIR2 8 (byte)
FIO1DIR3 8 (byte)
FIO1DIRL 16
(half-word)
FIO1DIRU 16
(half-word)
8.4.2 Fast GPIO port Mask register (FIOMASK, Port 0: FIO0MASK -
0x3FFF C010 and Port 1:FIO1MASK - 0x3FFF C030)
This register is available in the enhanced group of registers only. It is used to select port's
pins that will and will not be affected by a write accesses to the FIOPIN, FIOSET or
FIOSLR register. Mask register also filters out port's content when the FIOPIN register is
read.
A zero in this register's bit enables an access to the corresponding physical pin via a read
or write access. If a bit in this register is one, corresponding pin will not be changed with
write access and if read, will not be reflected in the updated FIOPIN register. For software
examples, see
Table 73: Fast GPIO port 0 Mask register (FIO0MASK - address 0x3FFF C010) bit description
Bit Symbol Value Description
31:0 FP0xMASK
0
1
Table 74: Fast GPIO port 1 Mask register (FIO1MASK - address 0x3FFF C030) bit description
Bit Symbol Value Description
31:0 FP1xMASK
0
1
User manual
Address Description
0x3FFF C020 Fast GPIO Port 1 Direction control register 0. Bit 0 in FIO1DIR0
register corresponds to P1.0 ... bit 7 to P1.7.
0x3FFF C021 Fast GPIO Port 1 Direction control register 1. Bit 0 in FIO1DIR1
register corresponds to P1.8 ... bit 7 to P1.15.
0x3FFF C022 Fast GPIO Port 1 Direction control register 2. Bit 0 in FIO1DIR2
register corresponds to P1.16 ... bit 7 to P1.23.
0x3FFF C023 Fast GPIO Port 1 Direction control register 3. Bit 0 in FIO1DIR3
register corresponds to P1.24 ... bit 7 to P1.31.
0x3FFF C020 Fast GPIO Port 1 Direction control Lower half-word register. Bit 0 in
FIO1DIRL register corresponds to P1.0 ... bit 15 to P1.15.
0x3FFF C022 Fast GPIO Port 1 Direction control Upper half-word register. Bit 0 in
FIO1DIRU register corresponds to P1.16 ... bit 15 to P1.31.
Section 8.5 "GPIO usage notes" on page 92
Fast GPIO physical pin access control.
Pin is affected by writes to the FIOSET, FIOCLR, and FIOPIN registers.
Current state of the pin will be observable in the FIOPIN register.
Physical pin is unaffected by writes into the FIOSET, FIOCLR and FIOPIN
registers. When the FIOPIN register is read, this bit will not be updated with
the state of the physical pin.
Fast GPIO physical pin access control.
Pin is affected by writes to the FIOSET, FIOCLR, and FIOPIN registers.
Current state of the pin will be observable in the FIOPIN register.
Physical pin is unaffected by writes into the FIOSET, FIOCLR and FIOPIN
registers. When the FIOPIN register is read, this bit will not be updated with
the state of the physical pin.
Rev. 01 — 15 August 2005
UM10139
Chapter 8: GPIO
Reset
value
0x00
0x00
0x00
0x00
0x0000
0x0000
Reset value
0x0000 0000
Reset value
0x0000 0000
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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