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Philips Semiconductors
Volume 1
User manual
Feed error
Feed
sequence
Feed OK
WDFEED
PLCK
WDTV
register
1. Counter is enabled only when the WDEN bit is set
and a valid feed sequence is done.
2. WDEN and WDRESET are sticky bits. Once set
they can't be cleared until the watchdog underflows or
an external reset occurs.
Fig 64. Watchdog block diagram
Rev. 01 — 15 August 2005
WDTC
32 BIT DOWN
/ 4
COUNTER
CURRENT WD
TIMER COUNT
WDMOD
2
WDEN
WDTOF
Register
UM10139
Chapter 20: WDT
Under
flow
Enable
1
count
SHADOW BIT
WDINT
WDRESET
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
2
Reset
Interrupt
290
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