A/D Global Start Register (Adgsr - 0Xe003 4008); A/D Status Register; Adc0: Ad0Cr - 0Xe003 4004 And Adc1: Ad1Cr - 0Xe006 0004) - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1

17.4.3 A/D Global Start Register (ADGSR - 0xE003 4008)

Software can write this register to simultaneously initiate conversions on both A/D
controllers. This register is available in LPC2144/6/8 devices only.
Table 257: A/D Global Start Register (ADGSR - address 0xE003 4008) bit description
Bit Symbol Value Description
15:0 -
16 BURST 1
0
23:17 -
26:24 START
000
001
010
011
100
101
110
111
27 EDGE
1
0
31:28 -
17.4.4 A/D Status Register (ADSTAT, ADC0: AD0CR - 0xE003 4004 and
ADC1: AD1CR - 0xE006 0004)
The A/D Status register allows checking the status of all A/D channels simultaneously.
The DONE and OVERRUN flags appearing in the ADDRn register for each A/D channel
are mirrored in ADSTAT. The interrupt flag (the logical OR of all DONE flags) is also found
in ADSTAT.
User manual
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
The AD converters do repeated conversions at the rate selected by their CLKS fields,
scanning (if necessary) through the pins selected by 1s in their SEL field. The first
conversion after the start corresponds to the least-significant 1 in the SEL field, then
higher numbered 1-bits (pins) if applicable. Repeated conversions can be terminated by
clearing this bit, but the conversion that's in progress when this bit is cleared will be
completed.
Important: START bits must be 000 when BURST = 1 or conversions will not start.
Conversions are software controlled and require 11 clocks.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
When the BURST bit is 0, these bits control whether and when an A/D conversion is
started:
No start (this value should be used when clearing PDN to 0).
Start conversion now.
Start conversion when the edge selected by bit 27 occurs on
P0.16/EINT0/MAT0.2/CAP0.2 pin.
Start conversion when the edge selected by bit 27 occurs on
P0.22/TD3/CAP0.0/MAT0.0 pin.
Start conversion when the edge selected by bit 27 occurs on MAT0.1.
Start conversion when the edge selected by bit 27 occurs on MAT0.3.
Start conversion when the edge selected by bit 27 occurs on MAT1.0.
Start conversion when the edge selected by bit 27 occurs on MAT1.1.
This bit is significant only when the START field contains 010-111. In these cases:
Start conversion on a falling edge on the selected CAP/MAT signal.
Start conversion on a rising edge on the selected CAP/MAT signal.
Reserved, user software should not write ones to reserved bits. The value read from a
reserved bit is not defined.
Rev. 01 — 15 August 2005
UM10139
Chapter 17: A/D Converter
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Reset
value
NA
0
NA
0
0
NA
269