Philips LPC214 Series User Manual page 336

Philips Semiconductors
Volume 1
0xE001 4000) bit description . . . . . . . . . . . . .259
Table 249:PWM Timer Control Register (PWMTCR -
address 0xE001 4004) bit description . . . . . .260
Table 250:Match Control Register (MCR, TIMER0: T0MCR -
address 0xE000 4014 and TIMER1: T1MCR -
address 0xE000 8014) bit description . . . . . .261
Table 251:PWM Control Register (PWMPCR - address
0xE001 404C) bit description . . . . . . . . . . . . .262
Table 252:PWM Latch Enable Register (PWMLER - address
0xE001 4050) bit description . . . . . . . . . . . . .264
Table 253:ADC pin description . . . . . . . . . . . . . . . . . . . .265
Table 254:ADC registers . . . . . . . . . . . . . . . . . . . . . . . . .266
Table 255:A/D Control Register (AD0CR - address
0xE003 4000 and AD1CR - address
0xE006 0000) bit description . . . . . . . . . . . . .267
Table 256:A/D Global Data Register (AD0GDR - address
0xE003 4004 and AD1GDR - address
0xE006 0004) bit description . . . . . . . . . . . . .268
Table 257:A/D Global Start Register (ADGSR - address
0xE003 4008) bit description . . . . . . . . . . . . .269
Table 258:A/D Status Register (ADSTAT, ADC0: AD0STAT -
address 0xE003 4004 and ADC1: AD1STAT -
address 0xE006 0004) bit description . . . . . .270
Table 259:A/D Status Register (ADSTAT, ADC0: AD0STAT -
address 0xE003 4004 and ADC1: AD1STAT -
address 0xE006 0004) bit description . . . . . .270
Table 260:A/D Data Registers (ADDR0 to ADDR7, ADC0:
AD0DR0 to AD0DR7 - 0xE003 4010 to 0xE003
402C and ADC1: AD1DR0 to AD1DR7- 0xE006
0010 to 0xE006 402C) bit description . . . . . .271
Table 261:DAC pin description . . . . . . . . . . . . . . . . . . . .273
Table 262:DAC Register (DACR - address 0xE006 C000) bit
description . . . . . . . . . . . . . . . . . . . . . . . . . . .273
Table 263:Real Time Clock (RTC) register map . . . . . . .276
Table 264:Miscellaneous registers . . . . . . . . . . . . . . . . .277
Table 265:Interrupt Location Register (ILR - address
0xE002 4000) bit description . . . . . . . . . . . . .278
Table 266:Clock Tick Counter Register (CTCR - address
0xE002 4004) bit description . . . . . . . . . . . . .278
Table 267:Clock Control Register (CCR - address
0xE002 4008) bit description . . . . . . . . . . . . .278
Table 268:Counter Increment Interrupt Register (CIIR -
address 0xE002 400C) bit description . . . . . .279
Table 269:Alarm Mask Register (AMR - address
0xE002 4010) bit description . . . . . . . . . . . . .279
Table 270:Consolidated Time register 0 (CTIME0 - address
0xE002 4014) bit description . . . . . . . . . . . . .280
Table 271:Consolidated Time register 1 (CTIME1 - address
0xE002 4018) bit description . . . . . . . . . . . . .280
Table 272:Consolidated Time register 2 (CTIME2 - address
0xE002 401C) bit description . . . . . . . . . . . . .280
User manual
Table 273:Time counter relationships and values. . . . . . 281
Table 274:Time counter registers . . . . . . . . . . . . . . . . . . 281
Table 275:Alarm registers. . . . . . . . . . . . . . . . . . . . . . . . 282
Table 276:Reference clock divider registers . . . . . . . . . . 283
Table 277:Prescaler Integer register (PREINT - address
0xE002 4080) bit description . . . . . . . . . . . . . 283
Table 278:Prescaler Integer register (PREFRAC - address
0xE002 4084) bit description . . . . . . . . . . . . . 283
Table 279:Prescaler cases where the Integer Counter reload
value is incremented . . . . . . . . . . . . . . . . . . . 285
Table 280:Recommended values for the RTC external
32 kHz oscillator C
Table 281:Watchdog register map . . . . . . . . . . . . . . . . . 288
Table 282:Watchdog operating modes selection . . . . . . 288
Table 283:Watchdog Mode register (WDMOD - address
0xE000 0000) bit description . . . . . . . . . . . . . 289
Table 284:Watchdog Timer Constant register (WDTC -
address 0xE000 0004) bit description . . . . . . 289
Table 285:Watchdog Feed register (WDFEED - address
0xE000 0008) bit description . . . . . . . . . . . . . 289
Table 286:Watchdog Timer Value register (WDTV - address
0xE000 000C) bit description. . . . . . . . . . . . . 289
Table 287:Flash sectors in LPC2141, LPC2142, LPC2144,
LPC2146 and LPC2148 . . . . . . . . . . . . . . . . . 296
Table 288:ISP command summary. . . . . . . . . . . . . . . . . 298
Table 289:ISP Unlock command. . . . . . . . . . . . . . . . . . . 298
Table 290:ISP Set Baud Rate command . . . . . . . . . . . . 298
Table 291:Correlation between possible ISP baudrates and
external crystal frequency (in MHz) . . . . . . . . 299
Table 292:ISP Echo command . . . . . . . . . . . . . . . . . . . . 299
Table 293:ISP Write to RAM command . . . . . . . . . . . . . 300
Table 294:ISP Read memory command. . . . . . . . . . . . . 300
Table 295:ISP Prepare sector(s) for write operation
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 301
Table 296:ISP Copy command . . . . . . . . . . . . . . . . . . . . 301
Table 297:ISP Go command. . . . . . . . . . . . . . . . . . . . . . 302
Table 298:ISP Erase sector command . . . . . . . . . . . . . . 302
Table 299:ISP Blank check sector command . . . . . . . . . 303
Table 300:ISP Read Part Identification number
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 301:LPC214x Part Identification numbers . . . . . . 303
Table 302:ISP Read Boot code version number
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 303
Table 303:ISP Compare command. . . . . . . . . . . . . . . . . 304
Table 304:ISP Return codes Summary . . . . . . . . . . . . . 304
Table 305:IAP Command Summary . . . . . . . . . . . . . . . . 306
Table 306:IAP Prepare sector(s) for write operation
command . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307
Table 307:IAP Copy RAM to Flash command . . . . . . . . 308
Table 308:IAP Erase sector(s) command . . . . . . . . . . . . 308
Table 309:IAP Blank check sector(s) command . . . . . . . 309
Rev. 01 — 15 August 2005
UM10139
Chapter 25: Supplementary information
components . . . . . . . 286
X1/X2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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