Philips LPC214 Series User Manual page 10

Philips Semiconductors
Volume 1
address decoding for each peripheral. All peripheral register addresses are word aligned
(to 32-bit boundaries) regardless of their size. This eliminates the need for byte lane
mapping hardware that would be required to allow byte (8-bit) or half-word (16-bit)
accesses to occur at smaller boundaries. An implication of this is that word and half-word
registers must be accessed all at once. For example, it is not possible to read or write the
upper byte of a word register separately.
Table 2:
VPB peripheral
0
1
2
User manual
VECTORED INTERRUPT CONTROLLER
(AHB PERIPHERAL #126)
(AHB PERIPHERAL #125)
(AHB PERIPHERAL #124)
(AHB PERIPHERAL #3)
(AHB PERIPHERAL #2)
(AHB PERIPHERAL #1)
(AHB PERIPHERAL #0)
Fig 4. AHB peripheral map
VPB peripheries and base addresses
Base address
0xE000 0000
0xE000 4000
0xE000 8000
Rev. 01 — 15 August 2005
Peripheral name
Watchdog timer
Timer 0
Timer 1
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
UM10139
Chapter 2: Memory map
0xFFFF F000 (4G - 4K)
0xFFFF C000
0xFFFF 8000
0xFFFF 4000
0xFFFF 0000
0xFFE1 0000
0xFFE0 C000
0xFFE0 8000
0xFFE0 4000
0xFFE0 0000
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