0X3Fff C03C) - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1
Table 88: Fast GPIO port 1 output Set byte and half-word accessible register description
Register Register
name length (bits)
& access
FIO1SET0 8 (byte)
FIO1SET1 8 (byte)
FIO1SET2 8 (byte)
FIO1SET3 8 (byte)
FIO1SETL 16
(half-word)
FIO1SETU 16
(half-word)
8.4.5 GPIO port output Clear register (IOCLR, Port 0: IO0CLR -
0xE002 800C and Port 1: IO1CLR - 0xE002 801C; FIOCLR, Port 0:
FIO0CLR - 0x3FFF C01C and Port 1: FIO1CLR - 0x3FFF C03C)
This register is used to produce a LOW level output at port pins configured as GPIO in an
OUTPUT mode. Writing 1 produces a LOW level at the corresponding port pin and clears
the corresponding bit in the IOSET register. Writing 0 has no effect. If any pin is configured
as an input or a secondary function, writing to IOCLR has no effect.
Legacy registers are the IO0CLR and IO1CLR, while the enhanced GPIOs are supported
via the FIO0CLR and FIO1CLR registers. Access to a port pins via the FIOCLR register is
conditioned by the corresponding FIOMASK register (see
Mask register (FIOMASK, Port 0: FIO0MASK - 0x3FFF C010 and Port 1:FIO1MASK -
0x3FFF
Table 89: GPIO port 0 output Clear register 0 (IO0CLR - address 0xE002 800C) bit description
Bit Symbol
31:0 P0xCLR
Table 90: GPIO port 1 output Clear register 1 (IO1CLR - address 0xE002 801C) bit description
Bit Symbol
31:0 P1xCLR
Table 91: Fast GPIO port 0 output Clear register 0 (FIO0CLR - address 0x3FFF C01C) bit description
Bit Symbol
31:0 FP0xCLR
User manual
Address Description
0x3FFF C038 Fast GPIO Port 1 output Set register 0. Bit 0 in FIO1SET0 register
corresponds to P1.0 ... bit 7 to P1.7.
0x3FFF C039 Fast GPIO Port 1 output Set register 1. Bit 0 in FIO1SET1 register
corresponds to P1.8 ... bit 7 to P1.15.
0x3FFF C03A Fast GPIO Port 1 output Set register 2. Bit 0 in FIO1SET2 register
corresponds to P1.16 ... bit 7 to P1.23.
0x3FFF C03B Fast GPIO Port 1 output Set register 3. Bit 0 in FIO1SET3 register
corresponds to P1.24 ... bit 7 to P1.31.
0x3FFF C038 Fast GPIO Port 1 output Set Lower half-word register. Bit 0 in
FIO1SETL register corresponds to P1.0 ... bit 15 to P1.15.
0x3FFF C03A Fast GPIO Port 1 output Set Upper half-word register. Bit 0 in
FIO1SETU register corresponds to P1.16 ... bit 15 to P1.31.
C030)").
Description
Slow GPIO output value Clear bits. Bit 0 in IO0CLR corresponds to P0.0 ... Bit
31 in IO0CLR corresponds to P0.31.
Description
Slow GPIO output value Clear bits. Bit 0 in IO1CLR corresponds to P1.0 ... Bit
31 in IO1CLR corresponds to P1.31.
Description
Fast GPIO output value Clear bits. Bit 0 in FIO0CLR corresponds to P0.0 ... Bit
31 in FIO0CLR corresponds to P0.31.
Rev. 01 — 15 August 2005
UM10139
Chapter 8: GPIO
Reset
value
0x00
0x00
0x00
0x00
0x0000
0x0000
Section 8.4.2 "Fast GPIO port
Reset value
0x0000 0000
Reset value
0x0000 0000
Reset value
0x0000 0000
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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