9.1 Features
9.2 Pin description
Table 95:
Pin
RXD0
TXD0
9.3 Register description
UART0 contains registers organized as shown in
(DLAB) is contained in U0LCR[7] and enables access to the Divisor Latches.
User manual
UM10139
Chapter 9: Universal Asynchronous Receiver/Transmitter 0
(UART0)
Rev. 01 — 15 August 2005
•
16 byte Receive and Transmit FIFOs
•
Register locations conform to '550 industry standard.
•
Receiver FIFO trigger points at 1, 4, 8, and 14 bytes.
•
Built-in fractional baud rate generator with autobauding capabilities.
•
Mechanism that enables software and hardware flow control implementation.
UART0 pin description
Type
Description
Input
Serial Input. Serial receive data.
Output
Serial Output. Serial transmit data.
Rev. 01 — 15 August 2005
User manual
Table
96. The Divisor Latch Access Bit
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
95