Gpio Port Direction Register; 0X3Fff C020 - Philips LPC214 Series User Manual

Philips Semiconductors
Volume 1
Table 66: GPIO register map (local bus accessible registers - enhanced GPIO features)
Generic Description
Name
FIODIR Fast GPIO Port Direction control register.
This register individually controls the
direction of each port pin.
FIOMASK Fast Mask register for port. Writes, sets,
clears, and reads to port (done via writes to
FIOPIN, FIOSET, and FIOCLR, and reads of
FIOPIN) alter or return only the bits enabled
by zeros in this register.
FIOPIN Fast Port Pin value register using FIOMASK.
The current state of digital port pins can be
read from this register, regardless of pin
direction or alternate function selection (as
long as pins is not configured as an input to
ADC). The value read is masked by ANDing
with FIOMASK. Writing to this register
places corresponding values in all bits
enabled by ones in FIOMASK.
FIOSET Fast Port Output Set register using
FIOMASK. This register controls the state of
output pins. Writing 1s produces highs at the
corresponding port pins. Writing 0s has no
effect. Reading this register returns the
current contents of the port output register.
Only bits enabled by ones in FIOMASK can
be altered.
FIOCLR Fast Port Output Clear register using
FIOMASK0. This register controls the state
of output pins. Writing 1s produces lows at
the corresponding port pins. Writing 0s has
no effect. Only bits enabled by ones in
FIOMASK0 can be altered.
[1]
8.4.1 GPIO port Direction register (IODIR, Port 0: IO0DIR - 0xE002 8008 and
Port 1: IO1DIR - 0xE002 8018; FIODIR, Port 0: FIO0DIR - 0x3FFF C000
and Port 1:FIO1DIR - 0x3FFF C020)
This word accessible register is used to control the direction of the pins when they are
configured as GPIO port pins. Direction bit for any pin must be set according to the pin
functionality.
Legacy registers are the IO0DIR and IO1DIR, while the enhanced GPIO functions are
supported via the FIO0DIR and FIO1DIR registers.
Table 67: GPIO port 0 Direction register (IO0DIR - address 0xE002 8008) bit description
Bit Symbol Value Description
31:0 P0xDIR
0
1
User manual
Reset value reflects the data stored in used bits only. It does not include reserved bits content.
Slow GPIO Direction control bits. Bit 0 controls P0.0 ... bit 30 controls P0.30.
Controlled pin is input.
Controlled pin is output.
Rev. 01 — 15 August 2005
Access Reset PORT0
[1]
value Address & Name
R/W 0x0000 0000 0x3FFF C000
FIO0DIR
R/W 0x0000 0000 0x3FFF C010
FIO0MASK
R/W 0x0000 0000 0x3FFF C014
FIO0PIN
R/W 0x0000 0000 0x3FFF C018
FIO0SET
WO 0x0000 0000 0x3FFF C01C
FIO0CLR
UM10139
Chapter 8: GPIO
PORT1
Address & Name

0x3FFF C020

FIO1DIR
0x3FFF C030
FIO1MASK
0x3FFF C034
FIO1PIN
0x3FFF C038
FIO1SET
0x3FFF C03C
FIO1CLR
Reset value
0x0000 0000
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
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