Holtek HT32F52342 User Manual page 8

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352
Quadrature Decoder ..................................................................................................................... 246
Output Stage ................................................................................................................................. 248
Update Management .................................................................................................................... 252
Single Pulse Mode ........................................................................................................................ 253
Asymmetric PWM Mode ............................................................................................................... 255
Timer Interconnection ................................................................................................................... 256
Trigger ADC Start.......................................................................................................................... 259
PDMA Request ............................................................................................................................. 259
Register Map ..................................................................................................................... 260
Register Descriptions ......................................................................................................... 261
Timer Counter Configuration Register - CNTCFR ....................................................................... 261
Timer Mode Configuration Register - MDCFR ............................................................................. 263
Timer Trigger Configuration Register - TRCFR ............................................................................ 266
Timer Counter Register - CTR ..................................................................................................... 267
Channel 0 Input Configuration Register - CH0ICFR .................................................................... 268
Channel 1 Input Configuration Register - CH1ICFR .................................................................... 270
Channel 2 Input Configuration Register - CH2ICFR .................................................................... 272
Channel 3 Input Configuration Register - CH3ICFR .................................................................... 274
Channel 0 Output Configuration Register - CH0OCFR ............................................................... 276
Channel 1 Output Configuration Register - CH1OCFR ............................................................... 278
Channel 2 Output Configuration Register - CH2OCFR ............................................................... 280
Channel 3 Output Configuration Register - CH3OCFR ............................................................... 282
Channel Control Register - CHCTR ............................................................................................. 284
Channel Polarity Configuration Register - CHPOLR .................................................................... 285
Timer PDMA/Interrupt Control Register - DICTR ......................................................................... 286
Timer Event Generator Register - EVGR ..................................................................................... 288
Timer Interrupt Status Register - INTSR ...................................................................................... 290
Timer Counter Register - CNTR................................................................................................... 293
Timer Prescaler Register - PSCR ................................................................................................ 294
Timer Counter Reload Register - CRR ........................................................................................ 295
Channel 0 Capture/Compare Register - CH0CCR ...................................................................... 296
Channel 1 Capture/Compare Register - CH1CCR ...................................................................... 297
Channel 2 Capture/Compare Register - CH2CCR ...................................................................... 298
Channel 3 Capture/Compare Register - CH3CCR ...................................................................... 299
Channel 0 Asymmetric Compare Register - CH0ACR ................................................................. 300
Channel 1 Asymmetric Compare Register - CH1ACR ................................................................. 301
Channel 2 Asymmetric Compare Register - CH2ACR ................................................................. 302
Channel 3 Asymmetric Compare Register - CH3ACR ................................................................. 303
15 Basic Function Timer (BFTM) .......................................................................... 304
Introduction ........................................................................................................................ 304
Features ............................................................................................................................. 304
Functional Description ....................................................................................................... 305
Repetitive Mode ............................................................................................................................ 305
One Shot Mode ............................................................................................................................. 306
Rev. 1.30 8 of 656 September 28, 2018