Holtek HT32F52342 User Manual page 77

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352
Bits Field
[8] WUPEN
[7] DMOSON
[3] LDOOFF
[2] LDOLCM
[0] BAKRST
Rev. 1.30
Descriptions
External WAKEUP Pin Enable
0: Disable WAKEUP pin function.
1: Enable WAKEUP pin function.
The Software can set the WUPEN bit as 1 to enable the WAKEUP pin function
before entering the power saving mode. When WUPEN = 1, a rising edge on the
WAKEUP pin wakes up the system from the power saving mode. As the WAKEUP
pin is active high, this bit will set an input pull down mode when the bit is high. The
corresponding register bits which should be properly setup are the PBPD[12] to 1 in
the PBPDR register, the PBPU [12] to 0 in the PBPUR register and the PBCFG12
[3:0] field to 0x0F in the GPBCFGHR register.
Note: This bit is reset by a system reset or a Backup Domain reset. Because this
bit is located in the Backup Domain, after reset activity there will be a delay until
the bit is active. The bit will not be active until the system reset finished and the
Backup Domain ISO signal has been disabled. This means that the bit can not be
immediately set by software after a system reset finished and the Backup domain
ISO signal disabled. The delay time needed is a minimum of three 32KHz clock
periods until the bit reset activity has finished.
DMOS Control
0: DMOS is OFF
1: DMOS is ON
A DMOS is implemented to provide an alternative voltage source for the 1.5 V power
domain when the CPU enters the Deep-Sleep mode (SLEEPDEEP = 1). The control
bit DMOSON is set by software and cleared by software or PORB. If the DMOSON
bit is set to 1, the LDO will automatically be turned off when the CPU enters the
Deep-Sleep mode.
LDO Operating Mode Control
0: The LDO operates in a low current mode when CPU enters the Deep-Sleep
mode (SLEEPDEEP = 1). The V
1: The LDO is turned off when the CPU enters the Deep-Sleep mode
(SLEEPDEEP=1). The V
Note: This bit is only available when the DMOSON bit is cleared to 0.
LDO Low Current Mode
0: The LDO is operated in normal current mode.
1: The LDO is operated in low current mode.
Note: This bit is only available when CPU is in the run mode. The LDO output
current capability will be limited at 10mA below and lower static current when
the LDOLCM bit is set. It is suitable for CPU is operated at lower speed
system clock to get a lower current consumption. This bit will be clear to 0
when the LDO is power down or V
Backup Domain Software Reset
0: No action
1: Backup Domain Software Reset is activated - includes all the related RTC and
PWRCU registers.
77 of 656
power is available.
DD15
power is not available.
DD15
power domain reset.
DD
September 28, 2018