Holtek HT32F52342 User Manual page 535

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352
Bits Field
[5] RXDR
[4] BII
[3] FEI
[2] PEI
[1] OEI
Rev. 1.30
Descriptions
RX Data Ready
0: Receive data register is empty
1: Received data in the receive data register is ready to read.
This bit is set by hardware when the content of the receive shift register RDR has
been transferred to the URDR register. It is cleared by a read to the URDR register.
An interrupt is generated if RXDRIE=1 in the URIER register.
Break Interrupt Indicator
This bit is set to 1 whenever the received data input is held in the "spacing state"
(logic 0) for longer than a full character transmission time, which is the total time of
"start bit" + "data bits" + "parity" + "stop bits" duration. Writing 1 to this bit clears the
flag.
Framing Error Indicator
This bit is set 1 whenever the received character does not have a valid "stop bit",
which means the stop bit following the last data bit or parity bit is detected as logic
0. Writing 1 to this bit clears the flag.
Parity Error Indicator
This bit is set to 1 whenever the received character does not have a valid "parity bit".
Writing 1 to this bit clears the flag.
Overrun Error Indicator
An overrun error will occur only after the receive data register is full and when
the next character has been completely received in the receive shift register. The
character in the receive shift register will be overwritten when an overrun event
occurs. But the data in the receive shift register will not be transferred to the
receive data register. The OEI bit is used to indicate the overrun event as soon as it
happens. Writing 1 to this bit clears the flag.
535 of 656 September 28, 2018