Holtek HT32F52342 User Manual page 201

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352
Discontinuous Conversion Mode
The A/D converter will operate in the Discontinuous Conversion Mode for channels group when
the A/D conversion mode bit field ADMODE [1:0] in the ADCCONV register is set to 0x3. The
group to be converted can have up to 8 channels and can be arranged in a specific sequence by
configuring the ADCLSTn registers where n ranges from 0 to 1. This mode is provided to convert
data for the group with a short sequence, named as the A/D conversion subgroup, each time a
trigger event occurs. The subgroup length is defined by the ADSUBL [2:0] field in the ADCCONV
register to specify the subgroup length. In the Discontinuous Conversion Mode the A/D converter
can be started by a software trigger, a comparator output transition event, an external EXTI event
or a TM event for the groups determined by the Trigger Control Register ADCTCR and the Trigger
Source Register ADCTSR.
In the Discontinuous Conversion Mode, the A/D Converter will start to convert the next n
conversions where the number n is the subgroup length defined by the ADSUBL field. When a
trigger event occurs, the channels to be converted with a specific sequence are specified in the
ADCLSTn registers. After n conversions have completed, the subgroup EOC interrupt raw flag
ADIRAWG in the ADCIRAW register will be asserted. The A/D converter will now not continue
to perform the next n conversions until the next trigger event occurs. The conversion cycle will end
after all the group channels, of which the total number is defined by the ADSEQL[2:0] bits in the
ADCCONV register, have finished their conversion, at which point the cycle EOC interrupt raw
flag ADIRAWC in the ADCIRAW register will be asserted. If a new trigger event occurs after all
the subgroup channels have all been converted, i.e., a complete conversion cycle has been finished,
the conversion will restart from the first subgroup.
Example:
A/D subgroup length = 3 (ADSUBL=2) and sequence length = 8 (ADSEQL=7), channels to be
converted = 2, 4, 7, 5, 6, 3, 0 and 1 - specific converting sequence as defined in the ADCLSTn
registers,
▄
Trigger 1: subgroup channels to be converted are CH2, CH4 and CH7 with the ADIRAWG flag
being asserted after subgroup EOC.
▄
Trigger 2: subgroup channels to be converted are CH5, CH6 and CH3 with the ADIRAWG flag
being asserted after subgroup EOC.
▄
Trigger 3: subgroup channels to be converted are CH0 and CH1 with the ADIRAWG flag
being asserted after subgroup EOC. Also a Cycle end of conversion (EOC) interrupt raw flag
ADIRAWC will be asserted.
▄
Trigger 4: subgroup channels to be converted are CH2, CH4 and CH7 with the ADIRAWG flag
being asserted - conversion sequence restarts from the beginning.
Rev. 1.30 201 of 656 September 28, 2018