Sci Contact Control Register - Ccr - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352
SCI Contact Control Register – CCR
This register specifies the SCI pin setting and clock selection.
Offset: 0x008
Reset value: 0x0000_0008
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
CLKSEL
Type/Reset RW 0
Bits Field
[7] CLKSEL
[3] CDIO
[2] CCLK
Rev. 1.30
30 29 28
22 21 20
14 13 12
6 5 4
Reserved
Descriptions
Card Clock Selection
0: The CCLK bit content is present on the external SCI_CLK pin
1: The clock output on the external SCI_CLK pin is sourced from the f
This bit is used to select the external SCI_CLK pin clock source. It is set and cleared
by the application program. It is recommended that to activate the clock at a known
level a certain value should be first programmed into the CCLK bit before the
CLKSEL bit is switched from 1 to 0.
SCI_DIO pin control
0: SCI_DIO pin is logic level 0
1: SCI_DIO pin in open-drain condition
This bit is available only when the SCIM bit in the CR register is cleared to 0 to
configure the SCI to operate in the Manual Transfer Mode. It is set and cleared by
application program to control the external SCI_DIO pin status in the Manual Mode.
Reading this bit will return the present status of the SCI_DIO pin.
SCI_CLK pin control.
0: SCI_CLK pin is logic level 0
1: SCI_CLK pin is logic level 1
This bit is available only when the SCIM bit in the CR register is cleared to 0 to
configure the SCI to operate in the Manual Transfer Mode. It is set and cleared by
application program to control the external SCI_CLK pin status in the Manual Mode.
Reading this bit will return the current value in the register and not the present status
of the external SCI_CLK pin. To ensure that the clock remains at a known level a
certain value should be first programmed into the CCLK bit before the CLKSEL bit is
switched from 1 to 0.
552 of 656
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
CDIO CCLK
RW 1 RW 0
25 24
17 16
9 8
1 0
Reserved
clock
PSC_CK
September 28, 2018