Usart Irda Control Register - Irdacr - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352
USART IrDA Control Register – IrDACR
This register is used to control the IrDA mode of USART.
Offset: 0x018
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset RW 0 RW
7
Reserved
Type/Reset
Bits Field
[15:8] IrDAPSC
[5] RXINV
[4] TXINV
[3] LB
[2] TXSEL
[1] IrDALP
Rev. 1.30
30 29 28
22 21 20
14 13 12
0 RW 0 RW
6 5 4
RXINV TXINV
RW 0 RW
Descriptions
IrDA Prescaler value
This field contains the 8-bit debounce prescaler value.
The debounce count-down counter is driven by the USART clock, named as CK_
USART. The counting period is specified by the IrDAPSC field. The IrDAPSC field
must be set to a value equal to or greater than 0x01 for normal debounce counter
operation. If the pulse width is less than the duration specified by the IrDAPSC field,
the pulse will be considered as glitch noise and discarded.
00000000: Reserved – can not be used.
00000001: CK_USART clock divided by 1
00000010: CK_USART clock divided by 2
00000011: CK_USART clock divided by 3
...
RX Signal Inverse Control
0: No inversion
1: RX input signal is inversed
TX Signal Inverse Control
0: No inversion
1: TX output signal is inversed
IrDA Loop Back Mode
0: Disable IrDA loop back mode
1: Enable IrDA loop back mode for self testing.
Transmit Select
0: Enable IrDA receiver
1: Enable IrDA transmitter
IrDA Low Power Mode
Select the IrDA operation mode.
0: Normal mode
1: IrDA low power mode
521 of 656
27 26
Reserved
19 18
Reserved
11 10
IrDAPSC
0 RW 0 RW 0 RW
3 2
LB TXSEL
0 RW 0 RW 0 RW
25 24
17 16
9 8
0 RW 0
1 0
IrDALP IrDAEN
0 RW 0
September 28, 2018