Holtek HT32F52342 User Manual page 4

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352
PLL Control Register - PLLCR ....................................................................................................... 99
AHB Configuration Register - AHBCFGR .................................................................................... 100
AHB Clock Control Register - AHBCCR ...................................................................................... 101
APB Configuration Register - APBCFGR ..................................................................................... 103
APB Clock Control Register 0 - APBCCR0 .................................................................................. 104
APB Clock Control Register 1 - APBCCR1 .................................................................................. 106
Clock Source Status Register - CKST ......................................................................................... 108
APB Peripheral Clock Selection Register 0 - APBPCSR0 ........................................................... 109
APB Peripheral Clock Selection Register 1 - APBPCSR1 ............................................................111
HSI Control Register - HSICR .......................................................................................................113
HSI Auto Trimming Counter Register - HSIATCR .........................................................................114
Low Power Control Register - LPCR ............................................................................................115
MCU Debug Control Register - MCUDBGCR ...............................................................................116
7 Reset Control Unit (RSTCU) .............................................................................. 119
Introduction ........................................................................................................................ 119
Functional Descriptions ..................................................................................................... 120
Power On Reset ........................................................................................................................... 120
System Reset ............................................................................................................................... 120
AHB and APB Unit Reset .............................................................................................................. 120
Register Map ..................................................................................................................... 121
Register Descriptions ......................................................................................................... 121
Global Reset Status Register - GRSR ......................................................................................... 121
AHB Peripheral Reset Register - AHBPRSTR ............................................................................. 122
APB Peripheral Reset Register 0 - APBPRSTR0 ........................................................................ 123
APB Peripheral Reset Register 1 - APBPRSTR1 ........................................................................ 125
8 General Purpose I/O (GPIO) ............................................................................... 127
Introduction ........................................................................................................................ 127
Features ............................................................................................................................. 128
Functional Descriptions ..................................................................................................... 128
Default GPIO Pin Configuration .................................................................................................... 128
General Purpose I/O - GPIO ........................................................................................................ 128
GPIO Locking Mechanism ............................................................................................................ 130
Register Map ..................................................................................................................... 130
Register Descriptions ......................................................................................................... 131
Port A Data Direction Control Register - PADIRCR ..................................................................... 131
Port A Input Function Enable Control Register - PAINER ............................................................ 132
Port A Pull-Up Selection Register - PAPUR ................................................................................. 133
Port A Pull-Down Selection Register - PAPDR ............................................................................ 134
Port A Open Drain Selection Register - PAODR .......................................................................... 135
Port A Output Current Drive Selection Register - PADRVR ......................................................... 136
Port A Lock Register - PALOCKR ................................................................................................ 137
Port A Data Input Register - PADINR ........................................................................................... 138
Rev. 1.30 4 of 656 September 28, 2018