32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F52342/HT32F52352
Master Controller
The MCTMs and GPTMs can be linked together internally for timer synchronisation or chaining.
When one MCTM is configured to be in the Master Mode, the MCTM Master Controller will
generate a Master Trigger Output (MTO) signal which can reset, restart, stop the Slave counter or
be a clock source of the Slave Counter. This can be selected by the MMSEL field in the MDCFR
register to trigger or drive another MCTM or GPTM which should be configured in the Slave
Mode.
Figure 84. Master MCTMn and Slave GPTMm Connection
The Master Mode Selection bits, MMSEL, in the MDCFR register are used to select the MTO
source for synchronising another slave MCTM or GPTM.
Figure 85. MTO Selection
For example, setting the MMSEL field to 0x5 is to select the CH1OREF signal as the MTO signal
to synchronise another slave MCTM or GPTM. For a more detailed description, refer to the related
MMSEL field definitions in the MDCFR register.
Rev. 1.30
MCTMn Master
MMSEL
MTO
TSE
UEV1G bit
Counter enable signal
Update Event 1
Channel 0 Capture/Compare event
CH0OREF
CH1OREF
CH2OREF
CH3OREF
321 of 656
GPTMm Slave
SMSEL
ITI
TRSEL
MTO
MMSEL
September 28, 2018
Need help?
Do you have a question about the HT32F52342 and is the answer not in the manual?