Holtek HT32F52342 User Manual page 16

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352
Bus Turn-around and Idle Cycles ................................................................................................. 616
AHB Transaction Width Conversion ............................................................................................. 617
EBI Bank Access .......................................................................................................................... 619
PDMA Request ............................................................................................................................. 620
Register Map ..................................................................................................................... 620
Register Descriptions ......................................................................................................... 620
EBI Control Register - EBICR ...................................................................................................... 620
EBI Status Register - EBISR ........................................................................................................ 622
EBI Address Timing Register - EBIATR ....................................................................................... 623
EBI Read Timing Register - EBIRTR ........................................................................................... 624
EBI Write Timing Register - EBIWTR ........................................................................................... 625
EBI Parity Register - EBIPR ......................................................................................................... 626
28 Inter-IC Sound (I
Introduction ........................................................................................................................ 627
Features ............................................................................................................................. 627
Functional Description ....................................................................................................... 628
I 2 S Master and Slave Mode .......................................................................................................... 628
I S Clock Rate Generator ............................................................................................................. 629
2
I 2 S Interface Format ...................................................................................................................... 631
FIFO Control and Arrangement .................................................................................................... 638
PDMA and Interrupt ...................................................................................................................... 639
Register Map ..................................................................................................................... 639
Register Descriptions ......................................................................................................... 640
I 2 S Control Register - I2SCR ........................................................................................................ 640
I 2 S Interrupt Enable Register - I2SIER ......................................................................................... 642
I S Clock Divider Register - I2SCDR ........................................................................................... 643
2
I 2 S TX Data Register - I2STXDR ................................................................................................. 644
I 2 S RX Data Register - I2SRXDR ................................................................................................. 644
I 2 S FIFO Control Register - I2SFCR ............................................................................................ 645
I 2 S Status Register - I2SSR ......................................................................................................... 646
I 2 S Rate Counter Value Register - I2SRCNTR ............................................................................ 648
29 Cyclic Redundancy Check (CRC) .................................................................... 649
Introduction ....................................................................................................................... 649
Features ............................................................................................................................. 650
Function Descriptions ........................................................................................................ 650
CRC Computation ......................................................................................................................... 650
Byte and Bit Reversal for CRC Computation ................................................................................ 650
CRC with PDMA ........................................................................................................................... 651
Register Map ..................................................................................................................... 651
Register Descriptions ......................................................................................................... 652
CRC Control Register - CRCCR .................................................................................................. 652
CRC Seed Register - CRCSDR ................................................................................................... 653
Rev. 1.30
2 S) ........................................................................................... 627
16 of 656 September 28, 2018