Timer Mode Configuration Register - Mdcfr - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352
Timer Mode Configuration Register – MDCFR
This register specifies the GPTM master and slave mode selection and single pulse mode.
Offset: 0x004
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[24] SPMSET
Rev. 1.30
30 29 28
Reserved
22 21 20
Reserved
14 13 12
Reserved
6 5 4
Reserved
Descriptions
Single Pulse Mode Setting
0: Counter counts normally irrespective of whether the update event occurred or
not.
1: Counter stops counting at the next update event and then the TME bit is
cleared by hardware.
263 of 656
27 26 25
19 18 17
MMSEL
RW 0 RW
11 10 9
SMSEL
RW 0 RW
3 2 1
September 28, 2018
24
SPMSET
RW 0
16
0 RW 0
8
0 RW 0
0
TSE
RW 0