Clock Controller; Figure 78. Mctm Clock Selection Source - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352

Clock Controller

The following describes the Timer Module clock controller which determines the internal prescaler
counter clock source.
▄
Internal APB clock f
The default internal clock source is the APB clock f
escaler when the slave mode is disabled. When the slave mode selection bits SMSEL are set to
0x4, 0x5 or 0x6, the internal APB clock f
▄
STIED
The counter prescaler can count during each rising edge of the STI signal. This mode can be
selected by setting the SMSEL field to 0x7 in the MDCFR register. Here the counter will act
as an event counter. The input event, known as STI here, can be selected by setting the TRSEL
field to an available value except the value of 0x0. When the STI signal is selected as the clock
source, the internal edge detection circuitry will generate a clock pulse during each STI signal
rising edge to drive the counter prescaler. It is important to note that if the TRSEL field is set to
0x0 to select the software UEV1G bit as the trigger source, then when the SMSEL field is set to
0x7, the counter will be updated instead of counting.
f
CLKIN
(Slave mode disable) CK_PSC
STIED
(Trigger events)
TRSEL
SMSEL
ECME

Figure 78. MCTM Clock Selection Source

Rev. 1.30
CLKIN
CLKIN
PSCR CRR
CK_CNT
CLK CLK
PSC Prescaler CNTR
Reset Reset
Overflow /
Start/Stop
UEV1G bit
Underflow
317 of 656
which is used to drive the counter pr-
CLKIN
is the counter prescaler driving clock source.
REPR
Repetition Down
Counter
Dec
TM_CNT
Slave Restart
mode trigger
Update Event 1
September 28, 2018