Table Of Contents - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352

Table of Contents

1 Introduction ........................................................................................................... 26
Overview .............................................................................................................................. 26
Features ............................................................................................................................... 27
Device Information ............................................................................................................... 32
Block Diagram ..................................................................................................................... 33
2 Document Conventions ....................................................................................... 34
3 System Architecture ............................................................................................. 35
Arm ® Cortex ® -M0+ Processor .............................................................................................. 35
Bus Architecture ................................................................................................................... 36
Memory Organization .......................................................................................................... 37
Memory Map ................................................................................................................................... 38
Embedded Flash Memory ............................................................................................................... 41
Embedded SRAM Memory ............................................................................................................. 41
AHB Peripherals ............................................................................................................................. 41
APB Peripherals ............................................................................................................................. 41
4 Flash Memory Controller (FMC) .......................................................................... 42
Introduction .......................................................................................................................... 42
Features ............................................................................................................................... 42
Functional Descriptions ....................................................................................................... 43
Flash Memory Map ......................................................................................................................... 43
Flash Memory Architecture ............................................................................................................. 44
Wait State Setting ........................................................................................................................... 44
Booting Configuration ..................................................................................................................... 45
Page Erase ..................................................................................................................................... 46
Mass Erase ..................................................................................................................................... 47
Word Programming ......................................................................................................................... 48
Option Byte Description .................................................................................................................. 49
Page Erase/Program Protection ..................................................................................................... 49
Security Protection .......................................................................................................................... 51
Register Map ....................................................................................................................... 52
Register Descriptions ........................................................................................................... 53
Flash Target Address Register - TADR .......................................................................................... 53
Flash Write Data Register - WRDR ............................................................................................... 54
Flash Operation Command Register - OCMR ............................................................................... 55
Flash Operation Control Register - OPCR ..................................................................................... 56
Flash Operation Interrupt Enable Register - OIER ........................................................................ 57
Flash Operation Interrupt and Status Register - OISR .................................................................. 58
Flash Page Erase/Program Protection Status Register - PPSR .................................................... 60
Flash Security Protection Status Register - CPSR ........................................................................ 61
Rev. 1.30 2 of 656 September 28, 2018