32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F52342/HT32F52352
Low Power Control Register – LPCR
This register specifies the low power control.
Offset:
0x300
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits
Field
[8]
USBSLEEP USB Sleep Software Control Enable
[0]
BKISO
Rev. 1.30
30
29
28
22
21
20
14
13
12
Reserved
6
5
4
Reserved
Descriptions
0: Disable
1: Enable USB Software Sleeping
Set and reset by software. Please refer to the Power Control Unit chapter for more
information.
Backup Domain Isolation Control
0: Backup domain is isolated from other power domain
1: Backup domain is accessible by other power domain
Set and reset by software. Please refer to the Power Control Unit chapter for more
information.
115 of 656
27
26
25
Reserved
19
18
17
Reserved
11
10
3
2
September 28, 2018
24
16
9
8
USBSLEEP
RW
0
1
0
BKISO
RW
0
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