Holtek HT32F52342 User Manual page 18

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352
List of Tables
Table 1. Series Features and Peripheral List .......................................................................................... 32
Table 2. Document Conventions ............................................................................................................. 34
Table 3. Register Map ............................................................................................................................. 39
Table 4. Flash Memory and Option Byte ................................................................................................. 44
Table 5. Relationship Between Wait State Cycle and HCLK .................................................................. 44
Table 6. Booting Modes .......................................................................................................................... 45
Table 7. Option Byte Memory Map ......................................................................................................... 49
Table 8. Access Permission of Protected Main Flash Page .................................................................... 50
Table 9. Access Permission When Security Protection is Enabled ......................................................... 51
Table 10. FMC Register Map .................................................................................................................. 52
Table 11. Operation Mode Definitions ..................................................................................................... 72
Table 12. Enter/Exit Power Saving Modes .............................................................................................. 73
Table 13. Power Status After System Reset ........................................................................................... 74
Table 14. PWRCU Register Map ............................................................................................................ 74
Table 15. Output Divider2 Value Mapping............................................................................................... 88
Table 16. Feedback Divider2 Value Mapping.......................................................................................... 88
Table 17. CKOUT Clock Source ............................................................................................................. 91
Table 18. CKCU Register Map ............................................................................................................... 92
Table 19. RSTCU Register Map ........................................................................................................... 121
Table 20. AFIO, GPIO and IO Pad Control Signal True Table............................................................... 129
Table 21. GPIO Register Map ............................................................................................................... 130
Table 22. AFIO Selection for Peripheral Map Example ......................................................................... 177
Table 23. AFIO Register Map ................................................................................................................ 177
Table 24. Exception Types .................................................................................................................... 182
Table 25. NVIC Register Map ............................................................................................................... 184
Table 26. EXTI Register Map ................................................................................................................ 188
Table 27. Data format in ADCDR [15:0] ................................................................................................ 203
Table 28. A/D Converter Register Map ................................................................................................. 205
Table 29. CMP Register Map ................................................................................................................ 224
Table 30. Counting Direction and Encoding Signals ............................................................................. 247
Table 31. Compare Match Output Setup .............................................................................................. 248
Table 32. GPTM Register Map ............................................................................................................. 260
Table 33. GPTM Internal Trigger Connection ....................................................................................... 266
Table 34. BFTM Register Map .............................................................................................................. 307
Table 35. Compare Match Output Setup .............................................................................................. 328
Table 36. Output Control Bits for Complementary Output with a Break Event Occurrence .................. 336
Table 37. Lock Level Table.................................................................................................................... 346
Table 38. MCTM Register Map ............................................................................................................. 348
Table 39. MCTM Internal Trigger Connection ....................................................................................... 354
Rev. 1.30 18 of 656 September 28, 2018