32-Bit Arm
®
Cortex
®
-M0+ MCU
HT32F52342/HT32F52352
SDA
SCL
Figure 137. START and STOP Condition
Data Validity
The data on the SDA line must be stable during the high period of the SCL clock. The SDA data
state can only be changed when the clock signal on the SCL line is in a low state.
SDA
SCL
Figure 138. Data Validity
Rev. 1.30
S
START Condition
Change of
Stable data line
data allowed
448 of 656
SDA
SCL
P
STOP Condition
September 28, 2018
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