Channel 3 Asymmetric Compare Register - Ch3Acr - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352
Channel 3 Asymmetric Compare Register – CH3ACR
This register specifies the timer channel 3 asymmetric compare value.
Offset: 0x0AC
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset RW 0 RW
7
Type/Reset RW 0 RW
Bits Field
[15:0] CH3ACV
Rev. 1.30
30 29 28
22 21 20
14 13 12
0 RW 0 RW
6 5 4
0 RW 0 RW
Descriptions
Channel 3 Asymmetric Compare Value
When channel 3 is configured as asymmetric PWM mode and the counter is
counting down, the value written is this register will be compared to the counter.
303 of 656
27 26
Reserved
19 18
Reserved
11 10
CH3ACV
0 RW 0 RW 0 RW
3 2
CH3ACV
0 RW 0 RW 0 RW
25 24
17 16
9 8
0 RW 0
1 0
0 RW 0
September 28, 2018