Features; Function Descriptions; Crc Computation; Byte And Bit Reversal For Crc Computation - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352

Features

▄
Support CRC16 polynomial: 0x8005, X
▄
Support CCITT CRC16 polynomial: 0x1021, X
▄
Support IEEE-802.3 CRC32 polynomial: 0x04C11DB7, X
+X 7 +X 5 +X 4 +X
▄
Support 1's complement, byte reverse & bit reverse operation on data and checksum
▄
Support byte, half-word & word data size
▄
Programmable CRC initial seed value
▄
CRC computation done in 1 AHB clock cycle for 8-bit data and 4 AHB clock cycles for 32-bit
data
▄
Support PDMA to complete a CRC computation of a block of memory

Function Descriptions

This unit only enables the calculation in the CRC16, CCITT CRC16 and IEEE-802.3 CRC32
polynomial. In this unit, the generator polynomial is fixed to the numeric values for those modes;
therefore, the CRC value based on other generator polynomials cannot be calculated.

CRC Computation

The CRC calculation unit has 32-bit write CRC data register (CRCDR) and read CRC checksum
register (CRCCSR). The CRCDR register is used to input new data (write access), and the
CRCCSR register is used to hold the result of the previous CRC calculation (read access). Each
write operation to the CRCDR register creates a combination of the previous CRC value (stored
in CRCCSR) and the new one. The CRC block diagram is shown as Figure 217. The CRC unit
calculates the CRC data register (CRCDR) value is basic on byte by byte and default byte and bit
order is big-endian. The CRCDR register can be accessed write by word, right-aligned half-word
and right-aligned byte. For the other registers only 32-bit access is allowed. The duration of the
computation depends on data width:
▄
4 AHB clock cycles for 32-bit data input
▄
2 AHB clock cycles for 16-bit data input
▄
1 AHB clock cycles for 8-bit data input

Byte and Bit Reversal for CRC Computation

The byte reordering and byte-level bit reversal operation can be occurred before the data is
used in the CRC calculation or after the CRC checksum output. They are configurable using the
corresponding setting field of the CRCCR register. These operations occur on word or half words
write. The hardware ignores the DATBYRV bit of the CRCRCR register with any byte writes but
the bit reversal setting DATBIRV are still applied to the byte. The Figure 218 is shown the byte and
bit reversal operation example.
Rev. 1.30
+X
16
2 +X+1
650 of 656
+X +1
15 2
16 +X 12 +X 5 +1
32 +X 26 +X 23 +X 22 +X 16 +X 12 +X 11 +X 10 +X 8
September 28, 2018