Clock Synchronization; Arbitration; Figure 143. Clock Synchronization During Arbitration; Figure 144. Two Master Arbitration Procedure - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352

Clock Synchronization

Only one master device can generate the SCL clock under normal operation. However when there
is more than one master trying to generate the SCL clock, the clock should be synchronized so
that the data output can be compared. Clock synchronization is performed using the wired-AND
connection of the I

Figure 143. Clock Synchronization during Arbitration

Arbitration

A master may start a transfer only if the I
masters generate a START signal at approximately the same time, an arbitration procedure will
occur.
Arbitration takes place on the SDA line and can continue for many bits. The arbitration procedure
gives a higher priority to the device that transmits serial data with a binary low bit (logic low).
Other master devices which want to transmit binary high bits (logic high) will lose the arbitration.
As soon as a master loses the arbitration, the I
register and generate an interrupt if the interrupt enable bit, ARBLSIEN, in the I2CIER register is
set to 1. Meanwhile, it stops sending data and listens to the bus in order to detect an I
When the stop signal is detected, the master which has lost the arbitration may try to access the bus
again.
SCL
Data
from
device 1
Data
from
device 2
SDA line

Figure 144. Two Master Arbitration Procedure

Rev. 1.30
C interface to the SCL line.
2
SCL from
device 1
SCL from
device 2
SCL on
I2C BUS
2
1
1
1
452 of 656
Start High
Wait
period
state
C bus line is in the free or idle mode. If two or more
2 C module will set the ARBLOS bit in the I2CSR
0 1
Device 1 loses arbitration
0 0 1
0 0 1
2 C stop signal.
1
1
September 28, 2018