Functional Descriptions; Counter Mode; Figure 74. Up-Counting Example - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352

Functional Descriptions

Counter Mode

Up-Counting
In this mode the counter counts continuously from 0 to the counter-reload value, which is defined
in the CRR register, in a count-up direction. Once the counter reaches the counter-reload value,
the Timer Module generates an overflow event and the counter restarts to count once again from
0. This action will continue repeatedly. The counting direction bit DIR in the CNTCFR register
should be set to 0 for the up-counting mode.
When an update event 1 is generated by setting the UEV1G bit in the EVGR register to 1, the
counter value will also be initialised to 0.
CK_PSC
CNT_EN
CK_CNT
CNTR
CRR
CRR Shadow Register
PSCR
PSCR Shadow Register
PSC_CNT
Counter Overflow
Update Event 1 Flag
Write a new value

Figure 74. Up-counting Example

Rev. 1.30
F2 F3 F4 F5
F5
F5
0
0
0
Update the new value
313 of 656
0 1 2
36
36
1
1
0 1 0 1 0
Software clearing
3
1 0 1
September 28, 2018