Holtek HT48RU80 Manual

I/o type 8-bit mcu

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Tools Information

FAQs

Application Note

HA0003E Communicating between the HT48 & HT46 Series MCUs and the HT93LC46 EEPROM

HA0004E HT48 & HT46 MCU UART Software Implementation Method

HA0013E HT48 & HT46 LCM Interface Design

HA0021E Using the I/O Ports on the HT48 MCU Series

Features

Operating voltage:

=4MHz: 2.2V~5.5V

SYS

=8MHz: 3.3V~5.5V

SYS

Low voltage reset function

56 bidirectional I/O lines (max.)

Two interrupt input

16-bit´2 programmable timer/event counter and

overflow interrupts with PFD outputs

8-bit´1 programmable timer/event counter

On-chip RC oscillator, external crystal and RC oscil-

lator

32768Hz crystal oscillator for timing purposes only

Watchdog Timer

16K´16 program memory ROM

General Description

The HT48RU80/HT48CU80 are 8-bit high performance,

RISC architecture microcontroller devices specifically

designed for multiple I/O control product applications.

The mask version HT48CU80 is fully pin and function-

ally compatible with the OTP version HT48RU80 de-

vice.

The advantages of low power consumption, I/O flexibil-

ity, timer functions, oscillator options, HALT and

Rev. 1.10

HT48RU80/HT48CU80

I/O Type 8-Bit MCU

576´8 data memory RAM

Universal Asynchronous Receiver/Transmitter

(UART)

HALT function and wake-up feature reduce power

consumption

16-level subroutine nesting

Up to 0.5ms instruction cycle with 8MHz system clock

at V

=5V

Bit manipulation instruction

16-bit table read instruction

63 powerful instructions

All instructions in one or two machine cycles

48-pin SSOP, 64-pin QFP package

wake-up functions, watchdog timer, buzzer driver, as

well as low cost, enhance the versatility of these devices

to suit a wide range of application possibilities such as

industrial control, consumer products, subsystem con-

trollers, etc.

The HT48CU80 is under development and will be avail-

able soon.

March 14, 2007

Table of Contents

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Summary of Contents for Holtek HT48RU80

Page 1 The mask version HT48CU80 is fully pin and function- industrial control, consumer products, subsystem con- ally compatible with the OTP version HT48RU80 de- trollers, etc. vice. The HT48CU80 is under development and will be avail- The advantages of low power consumption, I/O flexibil- able soon.
Page 2: Block Diagram
HT48RU80/HT48CU80 Block Diagram R T C O S C R T C O S C R T C O S C S Y S R T C O S C S Y S P C 0 / T X , P C 1 / R X P C 2 ~ P C 7 Rev.
Page 3: Pin Assignment
HT48RU80/HT48CU80 Pin Assignment H T 4 8 R U 8 0 / H T 4 8 C U 8 0 6 4 Q F P - A H T 4 8 R U 8 0 / H T 4 8 C U 8 0 4 8 S S O P - A Rev.
Page 4: Pin Description
HT48RU80/HT48CU80 Pin Description Pin Name Options Description Bidirectional 8-bit input/output port. Each bit can be configured as a wake-up Pull-high input by configuration option. Software instructions determine if the pin is a PA0~PA7 Wake-up CMOS output or input. Configuration options determine if all pins on this port...
Page 5 HT48RU80/HT48CU80 D.C. Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions ¾ f ¾ =4MHz Operating Voltage ¾ f ¾ =8MHz ¾ 3V No load, f =4MHz, Operating Current (Crystal OSC) UART disable ¾ ¾ 3V No load, f...
Page 6 HT48RU80/HT48CU80 A.C. Characteristics Ta=25°C Test Conditions Symbol Parameter Min. Typ. Max. Unit Conditions ¾ ¾ 2.2V~5.5V 4000 System Clock (Crystal OSC) SYS1 ¾ ¾ 3.3V~5.5V 8000 ¾ ¾ 2.2V~5.5V 4000 System Clock (RC OSC) SYS2 ¾ ¾ 3.3V~5.5V 8000 ¾...
Page 7: Functional Description
HT48RU80/HT48CU80 Functional Description Execution Flow When executing a jump instruction, conditional skip ex- ecution, loading register, subroutine call or return from The system clock for the microcontroller is derived from subroutine, initial reset, internal interrupt, external inter- either a crystal or an RC oscillator. The system clock is rupt or return from interrupts, the PC manages the pro- internally divided into four non-overlapping clocks.
Page 8 HT48RU80/HT48CU80 · Location 000H 8192´16 bits´2 banks, addressed by the Program Counter and table pointer. This area is reserved for program initialization. After a chip reset, the program always begins execution at lo- The BP register bit5 is used to select the ROM bank.
Page 9 HT48RU80/HT48CU80 Higher-order byte register (TBLH) is read only. The ta- The special function registers consist of an Indirect ad- ble pointer (TBLP) is a read/write register (07H), dressing register 0 (IAR0;00H), a Memory pointer regis- which indicates the table location. Before accessing ter 0 (MP0;01H), an Indirect addressing register 1...
Page 10 HT48RU80/HT48CU80 RAM Mapping Arithmetic and Logic Unit - ALU Status Register - STATUS This circuit performs 8-bit arithmetic and logic operations. This 8-bit register (0AH) contains the zero flag (Z), carry The ALU provides the following functions: flag (C), auxiliary carry flag (AC), overflow flag (OV), power down flag (PDF), and watchdog time-out flag ·...
Page 11 HT48RU80/HT48CU80 Bit No. Label Function C is set if an operation results in a carry during an addition operation or if a borrow does not take place during a subtraction operation, otherwise C is cleared. C is also affected by a ro- tate through carry instruction.
Page 12 HT48RU80/HT48CU80 Bit No. Label Function Controls the master (global) interrupt (1= enable; 0= disable) EEI0 Controls the external interrupt 0 (1= enable; 0= disable) ET0I Controls the Timer/Event Counter 0 interrupt (1= enable; 0= disable) ET1I Controls the Timer/Event Counter 1 interrupt (1= enable; 0= disable) EIF0 External interrupt 0 request flag (1= active;...
Page 13 HT48RU80/HT48CU80 The External Interrupt 1 request flag (EIF1), UART inter- cost effective solution. However, the frequency of os- rupt request flag (URF), Timer/Event Counter 2 interrupt cillation may vary with VDD, temperatures and the chip request flag (T2F), External Interrupt 1 bit (EEI1), and itself due to process variations.
Page 14 HT48RU80/HT48CU80 · All of the I/O ports maintain their original status. clock may still come from the instruction clock and oper- · ates in the same manner except that in the HALT state The PDF flag is set and the TO flag is cleared.
Page 15 HT48RU80/HT48CU80 TO PDF RESET Conditions RES reset during power-up RES reset during normal operation RES wake-up HALT WDT time-out during normal operation WDT wake-up HALT Note: ²u² stands for ²unchanged² Reset Circuit To guarantee that the system oscillator is started and Note: ²*²...
Page 16 HT48RU80/HT48CU80 The states of the registers are summarized in the following table. Reset WDT Time-out RES Reset RES Reset WDT Time-out Register (Power On) (Normal Operation) (Normal Operation) (HALT) (HALT)* TMR0H xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx uuuu uuuu...
Page 17 HT48RU80/HT48CU80 Timer/Event Counter tions to the TMR1H. Reading from the TMR1H will latch the contents of TMR1H and TMR1L counters to the des- Three timer/event counters (TMR0, TMR1, TMR2) are tination and the lower-order byte buffer, respectively. implemented in this microcontroller.
Page 18 HT48RU80/HT48CU80 Bit No. Label Function ¾ Unused bit, read as ²0² 0~2, 5 Defines the TMR0 active edge of the Timer/Event Counter 0 (0=active on low to high; 1=active on high to low) T0ON Enables or disables the Timer 0 counting (0=disable; 1=enable)
Page 19 HT48RU80/HT48CU80 cording to the transient edges. In the case of counter able the corresponding interrupt services. In the case of overflows, the Counter 0/1/2 is reloaded from the Timer/Event Counter 0/1/2 OFF condition, writing data Timer/Event Counter 0/1/2 preload register and issues to the Timer/Event Counter 0/1/2 preload register will the interrupt request just like the other two modes.
Page 20 HT48RU80/HT48CU80 Input/Output Ports For output function, CMOS is the only configuration. These control registers are mapped to locations 13H, There are 56 bidirectional input/output lines in the 15H, 17H, 19H, 1BH, 1DH and 26H. microcontroller, labeled from PA to PG, which are...
Page 21 HT48RU80/HT48CU80 PC0/TX Input/Output Ports PC1/RX Input/Output Ports Low Voltage Reset - LVR The relationship between V and V is shown below. The microcontroller provides a low voltage reset circuit in order to monitor the supply voltage of the device. If the supply voltage of the device is within the range 0.9V~V...
Page 22 UART Bus Serial Interface UART external pin interfacing To communicate with an external serial interface, the The HT48RU80/HT48CU80 devices contain an inte- internal UART has two external pins known as TX and grated full-duplex asynchronous serial communications RX. The TX pin is the UART transmitter pin, which can...
Page 23 HT48RU80/HT48CU80 UART Data Transfer Scheme ter with TIDLE set and then writing to the TXR regis- Only the RXR register is mapped onto the MCU Data ter. The flag is not generated when a data Memory, the Receiver Shift Register is not mapped...
Page 24 HT48RU80/HT48CU80 U S R R e g i s t e r · ¨ UCR1 register The NF flag is the noise flag. When this read only The UCR1 register together with the UCR2 register flag is ²0² it indicates a no noise condition. When are the two UART control registers that are used to set the flag is ²1²...
Page 25 HT48RU80/HT48CU80 ¨ TXBRK disabled it will empty the buffer so any character re- maining in the buffer will be discarded. In addition, The TXBRK bit is the Transmit Break Character bit. the baud rate counter value will be reset. When the When this bit is ²0²...
Page 26 HT48RU80/HT48CU80 ¨ TX pin will be controlled by the UART. Clearing the TXEN bit during a transmission will cause the trans- This bit enables or disables the receiver interrupt. If mission to be aborted and will reset the transmitter. this bit is equal to ²1² when the receiver overrun...
Page 27 HT48RU80/HT48CU80 The following tables show actual values of baud rate and error values for the two values of BRGH. Baud Rates for BRGH=0 Baud Rate =8MHz =7.159MHz =4MHz =3.579545MHz K/BPS Kbaud Error Kbaud Error Kbaud Error Kbaud Error ¾ ¾...
Page 28 HT48RU80/HT48CU80 · Clearing the UARTEN bit will disable the TX and RX UART transmitter pins and allow these two pins to be used as normal Data word lengths of either 8 or 9 bits, can be selected I/O pins. When the UART function is disabled the by programming the BNO bit in the UCR1 register.
Page 29 HT48RU80/HT48CU80 Set the TXEN bit to ensure that the TX pin is used the Receive Serial Shift Register, commonly known as a UART transmitter pin and not as an I/O pin. as the RSR. The data which is received on the RX external input pin, is sent to the data recovery block.
Page 30 HT48RU80/HT48CU80 STOPS bits. If the break is much longer than 13 bit The OERR flag can be cleared by an access to the times, the reception will be considered as complete USR register followed by a read to the RXR register.
Page 31 HT48RU80/HT48CU80 UART Interrupt Scheme wake-up, which is also a UART interrupt source, does flag is set, irrespective of the data last bit status. The not have an associated flag, but will generate a UART address detect mode and parity enable are mutually interrupt if the microcontroller is woken up by a low exclusive functions.
Page 32 HT48RU80/HT48CU80 then a falling edge on the RX pin will wake-up the The clock source of the BZ/BZ, can originate from the MCU from the Power Down Mode. Note that as it timer/event counter 0/1 overflow signal selected by con- takes 1024 system clock cycles after a wake-up, be- figuration options.
Page 33 HT48RU80/HT48CU80 Options The following table shows all kinds of options in this microcontroller. All of the options must be defined to ensure having proper functioning system. Options WDT clock source: WDT oscillator or f /4 or RTC oscillator or disable...
Page 34: Application Circuits
HT48RU80/HT48CU80 Application Circuits R C S y s t e m O s c i l l a t o r C r y s t a l S y s t e m O s c i l l a t o r...
Page 35 HT48RU80/HT48CU80 Instruction Set Summary Instruction Flag Mnemonic Description Cycle Affected Arithmetic ADD A,[m] Add data memory to ACC Z,C,AC,OV ADDM A,[m] Add ACC to data memory Z,C,AC,OV ADD A,x Add immediate data to ACC Z,C,AC,OV ADC A,[m] Add data memory to ACC with carry...
Page 36 HT48RU80/HT48CU80 Instruction Flag Mnemonic Description Cycle Affected Branch JMP addr Jump unconditionally None SZ [m] Skip if data memory is zero None SZA [m] Skip if data memory is zero with data movement to ACC None SZ [m].i Skip if bit i of data memory is zero None SNZ [m].i...
Page 37: Instruction Definition
HT48RU80/HT48CU80 Instruction Definition ADC A,[m] Add data memory and carry to the accumulator Description The contents of the specified data memory, accumulator and the carry flag are added si- multaneously, leaving the result in the accumulator. ACC ¬ ACC+[m]+C Operation Affected flag(s) ¾...
Page 38 HT48RU80/HT48CU80 AND A,[m] Logical AND accumulator with data memory Description Data in the accumulator and the specified data memory perform a bitwise logical_AND op- eration. The result is stored in the accumulator. ACC ¬ ACC ²AND² [m] Operation Affected flag(s) ¾...
Page 39 HT48RU80/HT48CU80 CLR [m].i Clear bit of data memory Description The bit i of the specified data memory is cleared to 0. [m].i ¬ 0 Operation Affected flag(s) ¾ ¾ ¾ ¾ ¾ ¾ CLR WDT Clear Watchdog Timer Description The WDT is cleared (clears the WDT). The power down bit (PDF) and time-out bit (TO) are cleared.
Page 40 HT48RU80/HT48CU80 CPLA [m] Complement data memory and place result in the accumulator Description Each bit of the specified data memory is logically complemented (1¢s complement). Bits which previously contained a 1 are changed to 0 and vice-versa. The complemented result is stored in the accumulator and the contents of the data memory remain unchanged.
Page 41 HT48RU80/HT48CU80 HALT Enter power down mode Description This instruction stops program execution and turns off the system clock. The contents of the RAM and registers are retained. The WDT and prescaler are cleared. The power down bit (PDF) is set and the WDT time-out bit (TO) is cleared.
Page 42 HT48RU80/HT48CU80 MOV A,x Move immediate data to the accumulator Description The 8-bit data specified by the code is loaded into the accumulator. ACC ¬ x Operation Affected flag(s) ¾ ¾ ¾ ¾ ¾ ¾ MOV [m],A Move the accumulator to data memory...
Page 43 HT48RU80/HT48CU80 Return from subroutine Description The program counter is restored from the stack. This is a 2-cycle instruction. Program Counter ¬ Stack Operation Affected flag(s) ¾ ¾ ¾ ¾ ¾ ¾ RET A,x Return and place immediate data in the accumulator...
Page 44 HT48RU80/HT48CU80 RLC [m] Rotate data memory left through carry Description The contents of the specified data memory and the carry flag are rotated 1 bit left. Bit 7 re- places the carry bit; the original carry flag is rotated into the bit 0 position.
Page 45 HT48RU80/HT48CU80 RRCA [m] Rotate right through carry and place result in the accumulator Description Data of the specified data memory and the carry flag are rotated 1 bit right. Bit 0 replaces the carry bit and the original carry flag is rotated into the bit 7 position. The rotated result is stored in the accumulator.
Page 46 HT48RU80/HT48CU80 SET [m] Set data memory Description Each bit of the specified data memory is set to 1. [m] ¬ FFH Operation Affected flag(s) ¾ ¾ ¾ ¾ ¾ ¾ SET [m]. i Set bit of data memory Description Bit i of the specified data memory is set to 1.
Page 47 HT48RU80/HT48CU80 SUB A,[m] Subtract data memory from the accumulator Description The specified data memory is subtracted from the contents of the accumulator, leaving the result in the accumulator. ACC ¬ ACC+[m]+1 Operation Affected flag(s) ¾ ¾ Ö Ö Ö Ö...
Page 48 HT48RU80/HT48CU80 SZ [m] Skip if data memory is 0 Description If the contents of the specified data memory are 0, the following instruction, fetched during the current instruction execution, is discarded and a dummy cycle is replaced to get the proper instruction (2 cycles).
Page 49 HT48RU80/HT48CU80 XOR A,[m] Logical XOR accumulator with data memory Description Data in the accumulator and the indicated data memory perform a bitwise logical Exclu- sive_OR operation and the result is stored in the accumulator. ACC ¬ ACC ²XOR² [m] Operation Affected flag(s) ¾...
Page 50: Package Information
HT48RU80/HT48CU80 Package Information 48-pin SSOP (300mil) Outline Dimensions Dimensions in mil Symbol Min. Nom. Max. ¾ ¾ ¾ ¾ C¢ ¾ ¾ ¾ ¾ ¾ ¾ ¾ 0° 8° Rev. 1.10 March 14, 2007...
Page 51 HT48RU80/HT48CU80 64-pin QFP (14´20) Outline Dimensions Dimensions in mm Symbol Min. Nom. Max. ¾ 18.80 19.20 ¾ 13.90 14.10 ¾ 24.80 25.20 ¾ 19.90 20.10 ¾ ¾ ¾ ¾ 0.40 ¾ 2.50 3.10 ¾ ¾ 3.40 ¾ ¾ 0.10 ¾...
Page 52: Product Tape And Reel Specifications
HT48RU80/HT48CU80 Product Tape and Reel Specifications Reel Dimensions SSOP 48W Symbol Description Dimensions in mm Reel Outer Diameter 330±1.0 Reel Inner Diameter 100±0.1 13.0+0.5 Spindle Hole Diameter -0.2 Key Slit Width 2.0±0.5 32.2+0.3 Space Between Flange -0.2 Reel Thickness 38.2±0.2 Rev.
Page 53 HT48RU80/HT48CU80 Carrier Tape Dimensions SSOP 48W Symbol Description Dimensions in mm Carrier Tape Width 32.0±0.3 Cavity Pitch 16.0±0.1 Perforation Position 1.75±0.1 Cavity to Perforation (Width Direction) 14.2±0.1 Perforation Diameter 2.0 Min. Cavity Hole Diameter 1.5+0.25 Perforation Pitch 4.0±0.1 Cavity to Perforation (Length Direction) 2.0±0.1...
Page 54 Copyright Ó 2007 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek as- sumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used...

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