Ebi Address Timing Register - Ebiatr - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352
EBI Address Timing Register – EBIATR
This register specifies the address timing setting for each bank.
Offset: 0x010
Reset value: 0x0000_0707
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[10:8] ADDRHOLD
[2:0] ADDRSETUP Address Setup Time
Rev. 1.30
30 29 28
22 21 20
14 13 12
Reserved
6 5 4
Reserved
Descriptions
Address Hold Time
Sets the number of cycles for which the address should be held on the EBI_AD
bus after the EBI_ALE signal is asserted. This field is allowed to be set to 0.
Sets the number of cycles for which the address is driven onto the EBI_AD bus
before the EBI_ALE signal is asserted. If set to 0, one cycle is inserted by the
hardware. The cycle unit is based on an HCLK clock period.
623 of 656
27 26
Reserved
19 18
Reserved
11 10
ADDRHOLD
RW 1 RW
3 2
ADDRSETUP
RW 1 RW
25 24
17 16
9 8
1 RW 1
1 0
1 RW 1
September 28, 2018