Register Descriptions; I 2 C Control Register - I2Ccr - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352

Register Descriptions

I C Control Register – I2CCR
2
This register specifies the corresponding I
Offset: 0x000 (0)
Reset value: 0x0000_2000
31
Type/Reset
23
Type/Reset
15
SEQFILTER
Type/Reset RW 0 RW
7
ADRM
Type/Reset RW 0
Bits Field
[15:14] SEQFILTER
[13] COMBFILTEREn
[12] ENTOUT
[10] DMANACK
Rev. 1.30
2 C function enable control.
30 29
22 21
14 13
COMBFILTEREn ENTOUT Reserved DMANACK RXDMAE TXDMAE
0 RW 1 RW
6 5
Reserved
Descriptions
SDA or SCL Input Sequential Filter Configuration Bits
00: Sequential filter disable
01: 1 PCLK glitch filter
1x: 2 PCLK glitch filter
Note: This setting would affect the frequency of SCL. Detail is described in
I2CSLPGR register.
SDA or SCL Input Combinational Filter Enable Bit
0: Combinational filter Disable
1: Combinational filter Enable
I 2 C Timeout Function Enable Control
0: Timeout Function disabled
1: Timeout Function enabled
This bit is used to enable or disable the I
bit is cleared to 0, the ENTOUT bit will be automatically cleared to 0 by
hardware. It is recommended that users have to properly configure the PSC
and TOUT fields in the I2CTOUT register before the timeout counter starts to
count by setting the ENOUT bit to 1.
DMA Mode NACK Control
0: No operation
1: The I 2 C master receiver module sends a NACK signal automatically after
receiving the last byte from the slave transmitter in the DMA mode
When the I2CEN bit is cleared to 0, the DMANACK bit is automatically cleared
to 0 by hardware.
462 of 656
28 27 26
Reserved
20 19 18
Reserved
12 11 10
0 RW
4 3 2
I2CEN GCEN
RW 0 RW
2 C timeout function. When the I2CEN
25 24
17 16
9 8
0 RW 0 RW 0
1 0
STOP AA
0 RW 0 RW 0
September 28, 2018