Adc Dma Request Register - Adcdmar - Holtek HT32F52342 User Manual

32-Bit Arm ® Cortex ® -M0+ MCU
HT32F52342/HT32F52352
ADC DMA Request Register – ADCDMAR
This register contains the ADC DMA request enable bits.
Offset: 0x090
Reset value: 0x0000_0000
31
Type/Reset
23
Type/Reset
15
Type/Reset
7
Type/Reset
Bits Field
[2] ADDMAC
[1] ADDMAG
[0] ADDMAS
Rev. 1.30
30 29 28
22 21 20
14 13 12
6 5 4
Reserved
Descriptions
ADC Cycle EOC DMA Request Enable Bit
0: ADC cycle end of conversion DMA request is disabled
1: ADC cycle end of conversion DMA request is enabled
ADC Subgroup EOC DMA Request Enable Bit
0: ADC subgroup end of conversion DMA request is disabled
1: ADC subgroup end of conversion DMA request is enabled
ADC Single EOC DMA Request Enable Bit
0: ADC single end of conversion DMA request is disabled
1: ADC single end of conversion DMA request is enabled
220 of 656
27 26
Reserved
19 18
Reserved
11 10
Reserved
3 2
ADDMAC ADDMAG
RW 0 RW
September 28, 2018
25 24
17 16
9 8
1 0
ADDMAS
0 RW 0